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Python Implementation of Pipelined Adc

This document discusses the behavior and performance of pipelined analog-to-digital converters (ADCs). It describes how errors like gain, offset, and charge injection affect the ideal transfer characteristic. Specifically, it notes that a gain greater than 2 can cause saturation, while a gain less than 2 shrinks the decision levels and requires more stages. The document analyzes different non-ideal cases involving gain errors at the sample-and-hold amplifier and individual stages.

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Surya Padma
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© © All Rights Reserved
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Download as PPT, PDF, TXT or read online on Scribd
461 views

Python Implementation of Pipelined Adc

This document discusses the behavior and performance of pipelined analog-to-digital converters (ADCs). It describes how errors like gain, offset, and charge injection affect the ideal transfer characteristic. Specifically, it notes that a gain greater than 2 can cause saturation, while a gain less than 2 shrinks the decision levels and requires more stages. The document analyzes different non-ideal cases involving gain errors at the sample-and-hold amplifier and individual stages.

Uploaded by

Surya Padma
Copyright
© © All Rights Reserved
Available Formats
Download as PPT, PDF, TXT or read online on Scribd
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PYTHON implementation of

‘Behavioural Pipelined ADC model’


as a function of possible errors
Overview on Pipelined
Performance characteristics
depends on …..
• Architecture
• Latency
• Digital error correction, Digital calibration
• Component accuracy

• 8-16 bit (100+Msps – Msps)


Ideal case

• Across all the stages • Gain Error =0


errors being zero • Offset Error =0
• Charge =0
Ideal Residue Plot
• X -> D(ll)D( 12) ... D( 17)
i.e, quantized representation of
the residue output Vout.

• The output D(lO)D(ll) ... D(17)


is identified as the quantized
representation of Vin.

• The digital output D(lO)D(ll) ...


D(17) is plotted as a function
of Vin, resulting in an ideal
transfer characteristic.

• Although D(lO)D(ll). .. D(17)


assumes discrete values, the
transfer characteristic is
plotted continuously for
simplicity.
Non-Ideal case

• Gain >2
<2
• Offset Error =0
• Charge Inj =0
• In case where the gain is greater
than 2, The max value of the
Robertson-plot of the MX2 stage
is a mathematically above the rail
voltage and we get stuck in the
pattern of 1s or zeros consistently
when similar stages forward the
electrical value

• Gain > 2 say 2.3(orange)


• Missing decision at a system level

• Gain < 2 say 1.7(red)


• Missing code at a system level

• Gain = 2 (green)
• Consistent
What is the price we pay for a
changed value of gain
• Gain > 2 pulls us into saturation at specific cases (i.e,. The
output of further stages stay at a recurring logic 0 or logic 1
even when the successive MX stages are ideal

• Gain < 2 shrinks the Robertson plot. Excessive gain


reduction decreases the total number of decision levels
available and requires an excessive number of additional
stages.
– Considering the aspects of mismatch in the circuits impacting
the performance, could lead to missing decisions and missing
codes when the gain of the stage is less than 2
Non-Ideality
Case 1 : Impact of gain error at SHA (gain>2)
Non-Ideality
Case 1 : Impact of gain error at SHA (gain<1)
Non-Ideality
Case 2 : Impact of gain error at MX2_1(>2) only
Non-Ideality
Case 2 : Impact of gain error at MX2_1(<2) only
Non-Ideality
Case 2 : Impact of gain error at MX2_2(>2) only
Non-Ideality
Case 2 : Impact of gain error at MX2_1(>2) & MX2_2(>2)
Ideal Residue Plot

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