Computer Organization and Architecture

Implementing MIPS
 We're ready to look at an implementation of the MIPS instruction set
 Simplified to contain only
 arithmetic-logic instructions: add, sub, and, or, slt
 memory-reference instructions: lw, sw
 control-flow instructions: beq, j

6 bits 5 bits 5 bits 5 bits 5 bits 6 bits

op rs rt rd shamt funct R-Format

6 bits 5 bits 5 bits 16 bits

op rs rt offset I-Format
6 bits 26 bits

op address J-Format
Implementing MIPS: the Fetch/Execute
Cycle
 High-level abstract view of fetch/execute implementation
 use the program counter (PC) to read instruction address
 fetch the instruction from memory and increment PC
 use fields of the instruction to select registers to read
 execute depending on the instruction
 repeat…
Overview: Processor Implementation
Styles
 Single Cycle
 perform each instruction in 1 clock cycle
 clock cycle must be long enough for slowest instruction; therefore,
 disadvantage: only as fast as slowest instruction
 Multi-Cycle
 break fetch/execute cycle into multiple steps
 perform 1 step in each clock cycle
 advantage: each instruction uses only as many cycles as it needs
 Pipelined
 execute each instruction in multiple steps
 perform 1 step / instruction in each clock cycle
 process multiple instructions in parallel – assembly line
State Elements on the Datapath:
Register File
 Registers are implemented with arrays of D-flipflops

Clock

5 bits
32 bits
5 bits

5 bits
32 bits
32 bits

Control signal

Register file with two read ports and

one write port
 State Elements on the Datapath:
Register File
Clock
 Port Clock
implementation:

Read ports are implemented Write port is implemented using

with a pair of multiplexors – 5 a decoder – 5-to-32 decoder for
bit multiplexors for 32 registers 32 registers. Clock is relevant to
write as register state may change
only at clock edge
Single-cycle Implementation of MIPS
 Our first implementation of MIPS will use a single long clock
cycle for every instruction
 Every instruction begins on one up (or, down) clock edge and
ends on the next up (or, down) clock edge
 This approach is not practical as it is much slower than a
multicycle implementation where different instruction classes
can take different numbers of cycles
 in a single-cycle implementation every instruction must take the
same amount of time as the slowest instruction
 in a multicycle implementation this problem is avoided by allowing
quicker instructions to use fewer cycles
 Even though the single-cycle approach is not practical it is
simple and useful to understand first

 Note : we shall implement jump at the very end

Datapath: Instruction Store/Fetch & PC
Increment

Three elements used to store

and fetch instructions and
increment the PC
Datapath
Animating the Datapath
Instruction <- MEM[PC]
PC <- PC + 4
 Datapath: R-Type Instruction

Two elements used to implement Datapath

R-type instructions
Animating the Datapath
add rd, rs, rt
R[rd] <- R[rs] + R[rt];
 Datapath:
Load/Store Instruction

Two additional elements used Datapath

To implement load/stores
Animating the Datapath
lw rt, offset(rs)
R[rt] <- MEM[R[rs] + s_extend(offset)];
Animating the Datapath
sw rt, offset(rs)
MEM[R[rs] + sign_extend(offset)] <- R[rt]
 Datapath: Branch Instruction
No shift hardware required:
simply connect wires from
input to output, each shifted
left 2 bits

Datapath
Animating the Datapath

beq rs, rt, offset

if (R[rs] == R[rt]) then

PC <- PC+4 + s_extend(offset<<2)
 MIPS Datapath I: Single-Cycle
Input is either register (R-type) or sign-extended
lower half of instruction (load/store)

Data is either
from ALU (R-type)
or memory (load) Combining the datapaths for R-type instructions
and load/stores using two multiplexors
Animating the Datapath:
R-type Instruction
add rd,rs,rt
Animating the Datapath:
Load Instruction
lw rt,offset(rs)
Animating the Datapath:
Store Instruction
sw rt,offset(rs)
 MIPS Datapath II: Single-Cycle
Separate adder as ALU operations and PC
increment occur in the same clock cycle

Separate instruction memory

as instruction and data read
occur in the same clock cycle
Adding instruction fetch
 MIPS Datapath III: Single-Cycle
New multiplexor

Extra adder needed as both

adders operate in each cycle

Instruction address is either

PC+4 or branch target address

Adding branch capability and another multiplexor

Important note: in a single-cycle implementation data cannot be stored
during an instruction – it only moves through combinational logic
Question: is the MemRead signal really needed?! Think of RegWrite…!
 Datapath Executing add

add rd, rs, rt

 Datapath Executing lw

lw rt,offset(rs)
 Datapath Executing sw

sw rt,offset(rs)
 Datapath Executing beq

beq r1,r2,offset
Control
 Control unit takes input from
 the instruction opcode bits

 Control unit generates

 ALU control input
 write enable (possibly, read enable also) signals for each storage
element
 selector controls for each multiplexor
 ALU Control
 Plan to control ALU: main control sends a 2-bit ALUOp control field to the ALU control. Based on ALUOp
and funct field of instruction the ALU control generates the 3-bit ALU control field

 ALU control Func- 2

field tion
ALUOp 3
000 and Main ALU To
001 or ALU ALU
Control Control
010 add control
110 sub
input
111 slt
6
 ALU must perform
 add for load/stores (ALUOp 00) Instruction
 sub for branches (ALUOp 01) funct field
 one of and, or, add, sub, slt for R-type instructions, depending on the instruction’s 6-bit funct field (ALUOp 10)
 Instruction AluOp Instruction Funct Field Desired ALU control
opcode operation ALU action input
LW 00 load word xxxxxx add 010
SW 00 store word xxxxxx add 010
Branch eq 01 branch eq xxxxxx subtract 110
R-type 10 add 100000 add 010
R-type 10 subtract 100010 subtract 110
R-type 10 AND 100100 and 000
R-type 10 OR 100101 or 001
R-type 10 set on less 101010 set on less 111

ALUOp Funct field Operation

ALUOp1 ALUOp0 F5 F4 F3 F2 F1 F0
0 0 X X X X X X 010
*Typo in text 0* 1 X X X X X X 110
Fig. 5.15: if it is X
1 X X X 0 0 0 0 010
then there is potential
1 X X X 0 0 1 0 110
conflict between
line 2 and lines 3-7! 1 X X X 0 1 0 0 000
1 X X X 0 1 0 1 001
1 X X X 1 0 1 0 111
Truth table for ALU control bits
 Designing the Main Control
R-type opcode rs rt rd shamt funct
31-26 25-21 20-16 15-11 10-6 5-0

Load/store
opcode rs rt address
or branch
31-26 25-21 20-16 15-0

 Observations about MIPS instruction format

 opcode is always in bits 31-26
 two registers to be read are always rs (bits 25-21) and rt (bits 20-16)
 base register for load/stores is always rs (bits 25-21)
 16-bit offset for branch equal and load/store is always bits 15-0
 destination register for loads is in bits 20-16 (rt) while for R-type
instructions it is in bits 15-11 (rd) (will require multiplexor to select)
 Datapath with Control I

New multiplexor

Adding control to the MIPS Datapath III (and a new multiplexor to select field to
specify destination register): what are the functions of the 9 control signals?
 Control Signals
Signal Name Effect when deasserted Effect when asserted

RegDst The register destination number for the The register destination number for the
Write register comes from the rt field (bits 20-16) Write register comes from the rd field (bits 15-11)
RegWrite None The register on the Write register input is written
with the value on the Write data input
AlLUSrc The second ALU operand comes from the The second ALU operand is the sign-extended,
second register file output (Read data 2) lower 16 bits of the instruction
PCSrc The PC is replaced by the output of the adder The PC is replaced by the output of the adder
that computes the value of PC + 4 that computes the branch target
MemRead None Data memory contents designated by the address
input are put on the first Read data output
MemWrite None Data memory contents designated by the address
input are replaced by the value of the Write data input
MemtoReg The value fed to the register Write data input The value fed to the register Write data input
comes from the ALU comes from the data memory

Effects of the seven control signals

 Datapath with Control II

MIPS datapath with the control unit: input to control is the 6-bit instruction
opcode field, output is seven 1-bit signals and the 2-bit ALUOp signal
 PCSrc cannot be
set directly from the
opcode: zero test
outcome is required

Datapath with
Control II (cont.)
Determining control signals for the MIPS datapath based on instruction opcode
Control Signals:
R-Type Instruction

0
Value depends on
??? funct
1
0
0

1
Control signals 0
shown in blue 0
Control Signals:
lw Instruction

0
010
0
0
1

1
Control signals 1
shown in blue 1
Control Signals:
sw Instruction

0
010
X
1
X

0
Control signals 1
shown in blue 0
Control Signals:
beq Instruction

1 if Zero=1
110
X
0
X

0
Control signals 0
shown in blue 0
 Datapath with Control III
Jump opcode address
31-26 Composing jump 25-0 New multiplexor with additional
target address control bit Jump

MIPS datapath extended to jumps: control unit generates new Jump control bit
Datapath Executing j
R-type Instruction: Step 1
add $t1, $t2, $t3 (active = bold)

Fetch instruction and increment PC count

R-type Instruction: Step 2
add $t1, $t2, $t3 (active = bold)

Read two source registers from the register file

R-type Instruction: Step 3
add $t1, $t2, $t3 (active = bold)

ALU operates on the two register operands

R-type Instruction: Step 4
add $t1, $t2, $t3 (active = bold)

Write result to register

Single-cycle Implementation Notes
 The steps are not really distinct as each instruction completes
in exactly one clock cycle – they simply indicate the sequence
of data flowing through the datapath
 The operation of the datapath during a cycle is purely
combinational – nothing is stored during a clock cycle
 Therefore, the machine is stable in a particular state at the
start of a cycle and reaches a new stable state only at the end
of the cycle
 Very important for understanding single-cycle computing:
See our simple Verilog single-cycle computer in the folder
SimpleSingleCycleComputer in Verilog/Examples
Load Instruction Steps
lw $t1, offset($t2)
1. Fetch instruction and increment PC
2. Read base register from the register file: the base register
($t2) is given by bits 25-21 of the instruction
3. ALU computes sum of value read from the register file and
the sign-extended lower 16 bits (offset) of the instruction
4. The sum from the ALU is used as the address for the data
memory
5. The data from the memory unit is written into the register
file: the destination register ($t1) is given by bits 20-16 of
the instruction
Load Instruction
lw $t1, offset($t2)
Branch Instruction Steps
beq $t1, $t2, offset
1. Fetch instruction and increment PC
2. Read two register ($t1 and $t2) from the register file
3. ALU performs a subtract on the data values from the
register file; the value of PC+4 is added to the sign-
extended lower 16 bits (offset) of the instruction shifted
left by two to give the branch target address
4. The Zero result from the ALU is used to decide which
adder result (from step 1 or 3) to store in the PC
Branch Instruction
beq $t1, $t2, offset
Implementation: ALU Control Block
ALUOp Funct field Operation
ALUOp1 ALUOp0 F5 F4 F3 F2 F1 F0
0 0 X X X X X X 010
0* 1 X X X X X X 110 *Typo in text
Fig. 5.15: if it is X
1 X X X 0 0 0 0 010
then there is potential
1 X X X 0 0 1 0 110 conflict between
1 X X X 0 1 0 0 000 line 2 and lines 3-7!
1 X X X 0 1 0 1 001
1 X X X 1 0 1 0 111
Truth table for ALU control bits

ALU control logic

 Implementation: Main Control Block
Signal R- lw sw beq
name format
Op5 0 1 1 0
Op4 0 0 0 0
Inputs

Op3 0 0 1 0
Op2 0 0 0 1
Op1 0 1 1 0
Op0 0 1 1 0
RegDst 1 0 x x
ALUSrc 0 1 1 0
MemtoReg 0 1 x x
RegWrite 1 1 0 0
Outputs

MemRead 0 1 0 0
MemWrite 0 0 1 0
Branch 0 0 0 1 Main control PLA (programmable
ALUOp1 1 0 0 0 logic array): principle underlying
ALUOP2 0 0 0 1 PLAs is that any logical expression
Truth table for main control signals can be written as a sum-of-products
 Single-Cycle Design Problems

 Assuming fixed-period clock every instruction datapath uses one

clock cycle implies:
 CPI = 1
 cycle time determined by length of the longest instruction path (load)
 but several instructions could run in a shorter clock cycle: waste of time
 consider if we have more complicated instructions like floating point!
 resources used more than once in the same cycle need to be
duplicated
 waste of hardware and chip area
 Example: Fixed-period clock vs.
variable-period clock in a
single-cycle implementation

 Consider a machine with an additional floating point unit. Assume functional unit delays
as follows
 memory: 2 ns., ALU and adders: 2 ns., FPU add: 8 ns., FPU multiply: 16 ns., register file
access (read or write): 1 ns.
 multiplexors, control unit, PC accesses, sign extension, wires: no delay
 Assume instruction mix as follows
 all loads take same time and comprise 31%
 all stores take same time and comprise 21%
 R-format instructions comprise 27%
 branches comprise 5%
 jumps comprise 2%
 FP adds and subtracts take the same time and totally comprise 7%
 FP multiplys and divides take the same time and totally comprise 7%
 Compare the performance of (a) a single-cycle implementation using a fixed-period clock with
(b) one using a variable-period clock where each instruction executes in one clock cycle that is
only as long as it needs to be (not really practical but pretend it’s possible!)
 Solution
Instruction Instr. Register ALU Data Register FPU FPU Total
class mem. read oper. mem. write add/ mul/ time
sub div ns.
Load word 2 1 2 2 1 8
Store word 2 1 2 2 7
R-format 2 1 2 0 1 6
Branch 2 1 2 5
Jump 2 2
FP mul/div 2 1 1 16 20
FP add/sub 2 1 1 8 12

 Clock period for fixed-period clock = longest instruction time = 20 ns.

 Average clock period for variable-period clock = 8  31% +
7  21% + 6  27% + 5  5% + 2  2% + 20  7% + 12  7%
= 7.0 ns.
 Therefore, performancevar-period /performancefixed-period = 20/7 = 2.9
Fixing the problem with single-cycle designs

 One solution: a variable-period clock with different cycle

times for each instruction class
 unfeasible, as implementing a variable-speed clock is
technically difficult
 Another solution:
use a smaller cycle time…
 …have different instructions take different numbers of cycles

by breaking instructions into steps and fitting each step into

one cycle
 feasible: multicyle approach!
Multicycle Approach
 Break up the instructions into steps
 each step takes one clock cycle
 balance the amount of work to be done in each step/cycle so that they are
about equal
 restrict each cycle to use at most once each major functional unit so that such
units do not have to be replicated
 functional units can be shared between different cycles within one instruction
 Between steps/cycles
 At the end of one cycle store data to be used in later cycles of the same
instruction
 need to introduce additional internal (programmer-invisible) registers for this
purpose
 Data to be used in later instructions are stored in programmer-visible state
elements: the register file, PC, memory
 Multicycle Approach

 Note particularities of
multicyle vs. single-
diagrams
 single memory for data
and instructions
 single ALU, no extra adders
 extra registers to
hold data between
clock cycles

Single-cycle datapath

Multicycle datapath (high-level view)

 Multicycle Datapath

Basic multicycle MIPS datapath handles R-type instructions and load/stores:

new internal register in red ovals, new multiplexors in blue ovals
Breaking instructions into steps
 Our goal is to break up the instructions into steps so that
 each step takes one clock cycle
 the amount of work to be done in each step/cycle is about equal
 each cycle uses at most once each major functional unit so that
such units do not have to be replicated
 functional units can be shared between different cycles within
one instruction
 Data at end of one cycle to be used in next must be stored !!
Breaking instructions into steps
 We break instructions into the following potential execution steps –
not all instructions require all the steps – each step takes one clock
cycle
1. Instruction fetch and PC increment (IF)
2. Instruction decode and register fetch (ID)
3. Execution, memory address computation, or branch completion (EX)
4. Memory access or R-type instruction completion (MEM)
5. Memory read completion (WB)

 Each MIPS instruction takes from 3 – 5 cycles (steps)

 Step 1: Instruction Fetch & PC
Increment (IF)

 Use PC to get instruction and put it in the instruction register.

Increment the PC by 4 and put the result back in the PC.

 Can be described succinctly using RTL (Register-Transfer Language):

IR = Memory[PC];
PC = PC + 4;
Step 2: Instruction Decode and Register Fetch (ID)

 Read registers rs and rt in case we need them.

Compute the branch address in case the instruction is a
branch.

 RTL:
A = Reg[IR[25-21]];
B = Reg[IR[20-16]];
ALUOut = PC + (sign-extend(IR[15-0]) << 2);
Step 3: Execution, Address Computation or
Branch Completion (EX)

 ALU performs one of four functions depending on instruction type

 memory reference:
ALUOut = A + sign-extend(IR[15-0]);
 R-type:
ALUOut = A op B;
 branch (instruction completes):
if (A==B) PC = ALUOut;
 jump (instruction completes):
PC = PC[31-28] || (IR(25-0) << 2)
Step 4: Memory access or R-type Instruction Completion
(MEM)

 Again depending on instruction type:

 Loads and stores access memory
 load
MDR = Memory[ALUOut];
 store (instruction completes)
Memory[ALUOut] = B;

 R-type (instructions completes)

Reg[IR[15-11]] = ALUOut;
Step 5: Memory Read Completion (WB)

 Again depending on instruction type:

 Load writes back (instruction completes)
Reg[IR[20-16]]= MDR;

Important: There is no reason from a datapath (or control) point

of view that Step 5 cannot be eliminated by performing
Reg[IR[20-16]]= Memory[ALUOut];
for loads in Step 4. This would eliminate the MDR as well.

The reason this is not done is that, to keep steps balanced in

length, the design restriction is to allow each step to contain at
most one ALU operation, or one register access, or one
memory access.
 Summary of Instruction
Execution
Step

1: IF

2: ID

3: EX

4: MEM

5: WB
 Multicycle Execution Step (1):
Instruction Fetch
IR = Memory[PC];
PC = PC + 4;

PC + 4
4
Multicycle Execution Step (2):
Instruction Decode & Register Fetch
A = Reg[IR[25-21]]; (A = Reg[rs])
B = Reg[IR[20-15]]; (B = Reg[rt])
ALUOut = (PC + sign-extend(IR[15-0]) << 2)

Branch
Reg[rs]
Target
Address

PC + 4

Reg[rt]
 Multicycle Execution Step (3):
Memory Reference Instructions
ALUOut = A + sign-extend(IR[15-0]);

Reg[rs] Mem.
Address

PC + 4

Reg[rt]
 Multicycle Execution Step (3):
ALU Instruction (R-Type)
ALUOut = A op B

Reg[rs]
R-Type
Result

PC + 4

Reg[rt]
 Multicycle Execution Step (3):
Branch Instructions
if (A == B) PC = ALUOut;

Branch
Reg[rs]
Target
Address

Branch
Target
Address
Reg[rt]
 Multicycle Execution Step (3):
Jump Instruction
PC = PC[31-28] concat (IR[25-0] << 2)

Branch
Reg[rs]
Target
Address

Jump
Address
Reg[rt]
 Multicycle Execution Step (4):
Memory Access - Read (lw)
MDR = Memory[ALUOut];

Reg[rs] Mem.
Address

PC + 4

Mem. Reg[rt]
Data
 Multicycle Execution Step (4):
Memory Access - Write (sw)
Memory[ALUOut] = B;

Reg[rs]

PC + 4

Reg[rt]
 Multicycle Execution Step (4):
ALU Instruction (R-Type)
Reg[IR[15:11]] = ALUOUT

Reg[rs]
R-Type
Result

PC + 4

Reg[rt]
 Multicycle Execution Step (5):
Memory Read Completion (lw)
Reg[IR[20-16]] = MDR;

Reg[rs]
Mem.
Address

PC + 4

Mem. Reg[rt]
Data
 Multicycle Datapath with Control I

… with control lines and the ALU control block added – not all control lines are shown
Multicycle Datapath with Control II
New gates New multiplexor
For the jump address

Complete multicycle MIPS datapath (with branch and jump capability)

and showing the main control block and all control lines
 Multicycle Control Step (1):
Fetch
IR = Memory[PC];
PC = PC + 4;
1

1
0 0 0
X 010

X
1 0
1
Multicycle Control Step (2):
Instruction Decode & Register Fetch
A = Reg[IR[25-21]]; (A = Reg[rs])
B = Reg[IR[20-15]]; (B = Reg[rt])
ALUOut = (PC + sign-extend(IR[15-0]) << 2);
0

0
X 0
0 X 010

X
0 0
3
 Multicycle Control Step (3):
Memory Reference Instructions
ALUOut = A + sign-extend(IR[15-0]);
0

0
X 1
0 X 010

X
0 0
2
 Multicycle Control Step (3):
ALU Instruction (R-Type)
ALUOut = A op B;
0

0
X 1
0 X ???

X
0 0
0
 Multicycle Control Step (3):
Branch Instructions
if (A == B) PC = ALUOut;
0

1 if
Zero=1
X 1
0 X 011

X
0 0
0
 Multicycle Execution Step (3):
Jump Instruction
PC = PC[21-28] concat (IR[25-0] << 2);
0

1
X X
0 X XXX

X
0 0
X
 Multicycle Control Step (4):
Memory Access - Read (lw)
MDR = Memory[ALUOut];
0

0
1 X
0 X XXX

X
1 0
X
 Multicycle Execution Steps (4)
Memory Access - Write (sw)
Memory[ALUOut] = B;

0
1 X
1 X XXX

X
0 0
X
 Multicycle Control Step (4):
ALU Instruction (R-Type)
Reg[IR[15:11]] = ALUOut; (Reg[Rd] =
ALUOut)
0
IRWrite

I Instruction I jmpaddr 28 32
0 R 5 I[25:0] <<2 CONCAT
PCWr* rs rt rd
2
X
IorD
32 5 5
0
MUX
1 RegDst
X M
0 5 1 ALUSrcA
XXX
1U
X
PC Operation 0
MemWrite RN1 RN2 WN 3
0M 0M
U ADDR M U PCSource
1X Registers 1X Zero
Memory D 0M RD1 A
RD R U
1X
WD ALU
ALU
X
OUT
WD RD2 B 0
MemRead MemtoReg 4 1M
U
2X
1 RegWrite
3

0 1 E
ALUSrcB
immediate 16 X 32
T <<2
N X
D
 Multicycle Execution Steps (5)
Memory Read Completion (lw)
Reg[IR[20-16]] = MDR;

IRWrite 0

I Instruction I jmpaddr 28 32
0 R 5 I[25:0] <<2 CONCAT
PCWr* rs rt rd
X 32
0 1 RegDst
X 2
M
IorD 0 5 5 MUX
5 0 ALUSrcA XXX 1U
X
PC Operation 0
MemWrite RN1 RN2 WN 3
0M 0M
U ADDR M U PCSource
1 X Registers 1X Zero
Memory D 0M RD1 A
RD R U
1X
WD ALU X
ALU
OUT
WD RD2 B 0
MemRead MemtoReg 4 1M
U
2X
0 RegWrite
3
0
immediate 16
1 E
X 32
ALUSrcB
T
N
<<2 X
D
Simple Questions
 How many cycles will it take to execute this code?

lw $t2, 0($t3)
lw $t3, 4($t3)
beq $t2, $t3, Label #assume not equal
add $t5, $t2, $t3
sw $t5, 8($t3)
Label: ...

 What is going on during the 8th cycle of execution?

 In what cycle does the actual addition of $t2 and $t3 takes place?

Clock time-line
 Implementing Control
 Value of control signals is dependent upon:
 what instruction is being executed
 which step is being performed

 Use the information we have accumulated to specify a finite

state machine
 specify the finite state machine graphically, or
 use microprogramming

 Implementation is then derived from the specification

 Review: Finite State Machines
 Finite state machines (FSMs):
 a set of states and
 next state function, determined by current state and the input
 output function, determined by current state and possibly input

 We’ll use a Moore machine – output based only on current state

 Example: Moore Machine
 The Moore machine below, given input a binary string terminated
by “#”, will output “even” if the string has an even number of 0’s
and “odd” if the string has an odd number of 0’s

Even state Odd state

1
0 1
No No
output output
0
Start

# #

Output Output
“even” “odd”

Output even state Output odd state

 FSM Control: High-level View

High-level view of FSM control

Asserted signals
shown inside
state circles

Instruction fetch and decode steps of every instruction is identical

FSM Control: Memory Reference

FSM control for memory-reference has 4 states

FSM Control: R-type Instruction

FSM control to implement R-type instructions has 2 states

FSM Control: Branch Instruction

FSM control to implement branches has 1 state

FSM Control: Jump Instruction

FSM control to implement jumps has 1 state

 FSM Control: Complete View
IF ID

EX

Labels on arcs are conditions

MEM that determine next state

WB
The complete FSM control for the multicycle MIPS datapath:
refer Multicycle Datapath with Control II
 Example: CPI in a multicycle CPU
 Assume
 the control design of the previous slide
 An instruction mix of 22% loads, 11% stores, 49% R-type operations, 16%
branches, and 2% jumps
 What is the CPI assuming each step requires 1 clock cycle?

 Solution:
 Number of clock cycles from previous slide for each instruction class:
 loads 5, stores 4, R-type instructions 4, branches 3, jumps 3
 CPI = CPU clock cycles / instruction count
= (instruction countclass i  CPIclass i) / instruction count
= (instruction countclass I / instruction count)  CPIclass I
= 0.22  5 + 0.11  4 + 0.49  4 + 0.16  3 + 0.02  3
= 4.04
FSM Control:
Implement-
ation

Four state bits are required for 10 states

High-level view of FSM implementation: inputs to the combinational logic block are
the current state number and instruction opcode bits; outputs are the next state
number and control signals to be asserted for the current state
 FSM
Control:
PLA
Implem-
entation

Upper half is the AND plane that computes all the products. The products are carried
to the lower OR plane by the vertical lines. The sum terms for each output is given by
the corresponding horizontal line
E.g., IorD = S0.S1.S2.S3 + S0.S1.S2.S3
 FSM Control: ROM Implementation

 ROM (Read Only Memory)

 values of memory locations are fixed ahead of time
 A ROM can be used to implement a truth table
 if the address is m-bits, we can address 2m entries in the ROM
 outputs are the bits of the entry the address points to
address output
0 0 0 0 0 1 1
m n
0 0 1 1 1 0 0
0 1 0 1 1 0 0
ROM m = 3 0 1 1 1 0 0 0
n = 4 1 0 0 0 0 0 0
1 0 1 0 0 0 1
1 1 0 0 1 1 0
1 1 1 0 1 1 1
The size of an m-input n-output ROM is 2m x n bits – such a ROM can
be thought of as an array of size 2m with each entry in the array being
n bits
FSM Control: ROM vs. PLA
 First improve the ROM: break the table into two parts
 4 state bits give the 16 output signals – 24 x 16 bits of ROM
 all 10 input bits give the 4 next state bits – 210 x 4 bits of ROM
 Total – 4.3K bits of ROM
 PLA is much smaller
 can share product terms
 only need entries that produce an active output
 can take into account don't cares
 PLA size = (#inputs  #product-terms) + (#outputs  #product-terms)
 FSM control PLA = (10x17)+(20x17) = 460 PLA cells
 PLA cells usually about the size of a ROM cell (slightly bigger)
Microprogramming

 Microprogramming is a method of specifying FSM control that resembles a

programming language – textual rather graphic
 this is appropriate when the FSM becomes very large, e.g., if the instruction set is
large and/or the number of cycles per instruction is large
 in such situations graphical representation becomes difficult as there may be
thousands of states and even more arcs joining them
 a microprogram is specification : implementation is by ROM or PLA
 A microprogram is a sequence of microinstructions
 each microinstruction has eight fields (label + 7 functional)
 Label: used to control microcode sequencing
 ALU control: specify operation to be done by ALU
 SRC1: specify source for first ALU operand
 SRC2: specify source for second ALU operand
 Register control: specify read/write for register file
 Memory: specify read/write for memory
 PCWrite control: specify the writing of the PC
 Sequencing: specify choice of next microinstruction
Microprogramming
 The Sequencing field value determines the execution order of
the microprogram
 value Seq : control passes to the sequentially next
microinstruction
 value Fetch : branch to the first microinstruction to begin the
next MIPS instruction, i.e., the first microinstruction in the
microprogram
 value Dispatch i : branch to a microinstruction based on control
input and a dispatch table entry (called dispatching):
 Dispatching is implemented by means of creating a table, called
dispatch table, whose entries are microinstruction labels and which is
indexed by the control input. There may be multiple dispatch tables
– the value Dispatch i in the sequencing field indicates that the i th
dispatch table is to be used
 Control Microprogram
 The microprogram corresponding to the FSM control shown
graphically earlier:

Microprogram containing 10 microinstructions

Dispatch ROM 1
Op Opcode name Value
Dispatch ROM 2
000000 R-format Rformat1
Op Opcode name Value
000010 jmp JUMP1 100011 lw LW2
000100 beq BEQ1
101011 sw SW2
100011 lw Mem1
101011 sw Mem1 Dispatch Table 2
Dispatch Table 1
 Microcode: Trade-offs
 Specification advantages
 easy to design and write
 typically manufacturer designs architecture and microcode in parallel
 Implementation advantages
 easy to change since values are in memory (e.g., off-chip ROM)
 can emulate other architectures
 can make use of internal registers
 Implementation disadvantages
 control is implemented nowadays on same chip as processor so the advantage of an off-chip ROM
does not exist
 ROM is no longer faster than on-board cache
 there is little need to change the microcode as general-purpose computers are used far more
nowadays than computers designed for specific applications
Summary
 Techniques described in this chapter to design datapaths and
control are at the core of all modern computer architecture
 Multicycle datapaths offer two great advantages over single-cycle
 functional units can be reused within a single instruction if they are
accessed in different cycles – reducing the need to replicate expensive
logic
 instructions with shorter execution paths can complete quicker by
consuming fewer cycles
 Modern computers, in fact, take the multicycle paradigm to a
higher level to achieve greater instruction throughput:
 pipelining (next topic) where multiple instructions execute
simultaneously by having cycles of different instructions overlap in the
datapath
 the MIPS architecture was designed to be pipelined