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    Pitch Matching: Chapter 1 Introduction

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    Carlos Saavedra
    Pitch matching is a technique used in chip layout where cells that connect have the same size along the connecting edge. This improves density by allowing cells to "snap together." Key to pitch matching is ensuring all connecting cells have the same pitch. The document discusses pitch matching of cells and provides examples, and summarizes how it was used in the layout of a MIPS datapath circuit.

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    Pitch Matching: Chapter 1 Introduction

    Uploaded by

    Carlos Saavedra
    95 views1 page
    Pitch matching is a technique used in chip layout where cells that connect have the same size along the connecting edge. This improves density by allowing cells to "snap together." Key to pitch matching is ensuring all connecting cells have the same pitch. The document discusses pitch matching of cells and provides examples, and summarizes how it was used in the layout of a MIPS datapath circuit.

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    CMOS-VLSI-design-77

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    Pitch matching is a technique used in chip layout where cells that connect have the same size along the connecting edge. This improves density by allowing cells to "snap together." Key to pitch matching is ensuring all connecting cells have the same pitch. The document discusses pitch matching of cells and provides examples, and summarizes how it was used in the layout of a MIPS datapath circuit.

    Copyright:

    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd
    Download as pdf or txt
    95 views1 page

    Pitch Matching: Chapter 1 Introduction

    Uploaded by

    Carlos Saavedra
    Pitch matching is a technique used in chip layout where cells that connect have the same size along the connecting edge. This improves density by allowing cells to "snap together." Key to pitch matching is ensuring all connecting cells have the same pitch. The document discusses pitch matching of cells and provides examples, and summarizes how it was used in the layout of a MIPS datapath circuit.

    Copyright:

    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd
    Download as pdf or txt
    of 1

    50 Chapter 1 Introduction

    A A A A B 1.10.3 Pitch Matching


    A A A A B The area of the controller in Figure 1.64 is dominated by the routing channels. When the
    A A A A B logic is more regular, layout density can be improved by including the wires in cells that
    A A A A B
    “snap together.” Snap-together cells require more design and layout effort but lead to
    smaller area and shorter (i.e., faster) wires. The key issue in designing snap-together cells
    C C D is pitch-matching. Cells that connect must have the same size along the connecting edge.
    Figure 1.66 shows several pitch-matched cells. Reducing the size of cell D does not help
    the layout area. On the other hand, increasing the size of cell D also affects the area of B
    FIGURE 1.66 Pitch-matching
    and/or C.
    of snap-together cells
    Figure 1.67 shows the MIPS datapath in more detail. The eight horizontal bitslices
    are clearly visible. The zipper at the top of the layout includes three rows for the decoder
    that is pitch-matched to the register file in the datapath. Vertical metal2 wires are used for
    control, including clocks, multiplexer selects, and register enables. Horizontal metal3
    wires run over the tops of cells to carry data along a bitslice.
    The width of the transistors in the cells and the number of wires that must run over
    the datapath determines the minimum height of the datapath cells. 60–100 Q are typical
    heights for relatively simple datapaths. The width of the cell depends on the cell contents.

    1.10.4 Slice Plans


    Figure 1.68 shows a slice plan of the datapath. The diagram illustrates the ordering of
    wordslices and the allocation of wiring tracks within each bitslice. Dots indicate that a bus
    passes over a cell and is also used in that cell. Each cell is annotated with its type and
    width (in number of tracks). For example, the program counter (pc) is an output of the
    PC flop and is also used as an input to the srcA and address multiplexers. The slice plan

    FIGURE 1.67 MIPS datapath layout

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