Computer Organization & Architecture

Dr. Muhammad Usman

Assistant Professor,
Department of Electrical Engineering,
U.E.T. Mardan

[Adapted from Dave Patterson’s UCB CS152 slides, Mary Jane Irwin’s PSU CSE331 slides and Dan
Garcia, Lectures SOE UC Berkeley]

Computer Organization & Architecture .1 Spring 2019

 Course Contents
 Computer Abstractions and Technology
 Performance Evaluation

 Language of the Computer

 Arithmetic for Computers
 Processor Design: Datapath & Control
 Enhancing Performance with Pipelining

 Memory Hierarchy
 Parallel Processing and Multicore Computing

Computer Organization & Architecture .2 Spring 2019

 Course Information

 Course: SE-205 Computer Organization & Architecture

• Core subject

 Instructor: Dr. Muhammad Usman

 usman@uetmardan.edu.pk

 Text Books:
 David A. Patterson, and John L. Hennessy, “Computer Organization
and Design: The Hardware/Software Interface”, 5th Edition, Elsevier
(Morgan Kaufmann Publishers)
 William Stallings, “Computer Organization and Architecture: Designing
for Performance”, 8th Edition, Pearson (Prentice Hall Publishers)

Computer Organization & Architecture .3 Spring 2019

 Convention

 Every class
 First 5-10 minutes, review of the last class

 Students will be randomly picked to answer questions

 Class participation is very important

Computer Organization & Architecture .4 Spring 2019

 Course Learning Outcomes

Acquire the basic knowledge of computer

CLO-1 organization, computer architecture and assembly PLO-1
language

Understand the concepts related to structure and

functioning of a digital computer, including its
CLO-2 PLO-1
overall system architecture, and digital
components.

Solve the problems related to computer

CLO-3 PLO-3
architecture/ organization and assembly language

Computer Organization & Architecture .5 Spring 2019

 What You Should Already Know
 How to write, compile and run programs in a higher level
language (C, C++, Java, …)
 How to represent and operate on positive and negative
numbers in binary form (two’s complement, sign
magnitude, etc.)
 Logic design
 How to design combinational and sequential components
(Boolean algebra, logic minimization, mapping, decoders and
multiplexors, latches and flipflops, registers, mealy/moore finite
state machines, state assignment and minimization, etc.)

Computer Organization & Architecture .6 Spring 2019

 Grading Information
 Grade determinates
 Midterm 25%
 Final Exam 50%
 Assignments 15%
 Quizzes 10%

 Repeaters students:
 If there is a conflict in timings with other class(es),
please sort it out yourself with the semester
coordinator.

Computer Organization & Architecture .7 Spring 2019

 Computer Architecture & Organization

 Computer Architecture refers to those attributes

visible to the programmer
 Instruction set, number of bits used for data
representation, I/O mechanisms, addressing techniques.
 e.g. Is there a multiply instruction?
 Direct impact on logical execution of the program

 Computer Organization refers to the operational

units and their interconnections that realize the
architectural specifications.
 Control signals, interfaces, memory technology.
 e.g. Is there a hardware multiply unit or is it done by
repeated addition?

Computer Organization & Architecture .8 Spring 2019

 Computer Architecture & Organization

 All Intel x86 family share the same basic architecture

 The IBM System/370 family share the same basic
architecture

 This gives code compatibility

 At least backwards

 Organization differs between different versions

Computer Organization & Architecture .9 Spring 2019

 Head’s Up

 This week’s material

 Course introduction
- Reading assignment – chapter 1, Appendix A,B & D

Computer Organization & Architecture .10 Spring 2019

 Outline of today’s Lecture
 Technology Trends
 Classes of Computers
 CISC Vs RISC
 Below your program
 From high level language to the language of hardware

 Parts of Computer

Computer Organization & Architecture .11 Spring 2019

 Technology Trends:
Microprocessor Complexity
# of transistors on an IC

Gordon Moore
Intel Cofounder
B.S. Cal 1950!

2XTransistors / Chip
Every 1.5 years

Called “Moore’s Law”

Year Spring 2019

Computer Organization & Architecture .12
 Technology Trends:
Memory Capacity (Single-Chip DRAM)
size

1000000000
year size (Mbit)
100000000 1980 0.0625
10000000 1983 0.25
1986 1
Bits
Bits

1000000

1989 4
100000
1992 16
10000
1996 64
1000
1998 128
1970 1975 1980 1985 1990 1995 2000

Year
Year 2000 256
• Now 1.4X/yr, or 2X every 2 years. 2002 512
• 8000X since 1980! 2004 1024 (1Gbit)
Computer Organization & Architecture .13 Spring 2019
 Technology Trends:
Uniprocessor Performance (SPECint)
VAX-11/780)

10000

1.20x/year
20%/year
1000
VAX-11/780)

1.52x/year
52%/year
(x86(vs.vs.

100
Performance
Performance

10
1.25x/year
25%/year

1
1978 1980 1982 1984 1986 1988 1990 1992 1994 1996 1998 2000 2002 2004 2006

• VAX : 1.25x/year 1978 to 1986

• RISC + x86: 1.52x/year 1986 to 2002
• RISC + x86: 1.20x/year 2002 to present
Computer Organization & Architecture .14 Spring 2019
 Computer Technology - Dramatic Change!
 Memory
 DRAM capacity: 2x / 2 years (since ‘96);
64x size improvement in last decade.

 Processor
 Speed 2x / 1.5 years(since ‘85);
100X performance in last decade.

 Disk
 Capacity: 2x / 1 year (since ‘97)
250X size in last decade.

 Moore’s Law enables processor

(2X transistors/chip ~1.5-2 yrs)

Computer Organization & Architecture .15 Spring 2019

 Computer Types
 Desktop/Laptop
 Dell Dimension, Dell OptiPlex
 Most widely used in everyday life

 Workstation
 Dell Precision, Sun Blade, IBM Intell-iStation
 Same dimensions as desktop computers
 High-resolution graphics I/O capability, more computational power

 Servers ~ Supercomputers
 HP Integrity Superdome, IBM eServer
 Computing power and storage

 Embedded Computers

Computer Organization & Architecture .16 Spring 2019

 • An embedded system is a
computer system with a
dedicated function within a
larger mechanical or electrical
system, often with real-time
computing constraints.
• It is embedded as part of a
complete device often
including hardware and
mechanical parts.

 The micro-controller is embedded in the appliance, you often are not aware of the
fact that it contains a micro-controller (e.g. 70 micro-controllers in a modern high
end car: engine control, ABS, airbag, interior illumination, central lock, alarm,
radio, ...)

Computer Organization & Architecture .17 Spring 2019

Computer Organization & Architecture .18 Spring 2019
 Processor Categories

 Popular processor designs can be broadly divided into two

categories:
 Complex Instruction Set Computer (CISC)
 Reduced Instruction Set Computers (RISC)

Computer Organization & Architecture .19 Spring 2019

 CISC
 Uses complex instruction
 For example an instruction is considered a complex
instruction which copies an element from one array to
another and automatically updates both array
subscripts.

 1970s & 80s processors followed CISC design

 Most PC's use CPU based on this architecture
 The dominant processor in the PC market, Pentium, and
AMD CPU's belongs to the CISC category.

Computer Organization & Architecture .20 Spring 2019

 Shift from earlier CISC to current RISC
 Memory was expensive and small in capacity
 In mid of 1970s, 16kB memory cost $500.
 An implication of the minimum memory usage is that each
processor instruction must do more, leading to complex instruction
set designs.

 Complex instructions meant complex hardware, which was

also expensive.
 How could a processor be designed that could execute
complex instructions using the technology of the day?
 This was a problem processor designers grappled with until
Wilkes proposed micro-programmed control
 A small run-time interpreter that takes the complex instruction and
generates a sequence of simple instructions that can be executed
by the hardware.

Computer Organization & Architecture .21 Spring 2019

Computer Organization & Architecture .22 Spring 2019
 RISC
 Reduced Instruction Set Computer. RISC evolved around
the mid-1980 as competitor of CISC.
 Fewer, simpler and faster instructions would be better,
than the large, complex and slower CISC instructions.
However, more instructions are needed to accomplish a
task.
 Another advantage of RISC is that because of the more
simple instructions, RISC chips require fewer transistors,
which makes them easier to design and cheaper to produce
 RISC usually load/store architecture
 Only these two instructions are for accessing memory
 RISC systems assume that the required operands are in the
processor’s internal registers, not in the main memory.

Computer Organization & Architecture .23 Spring 2019

  RISC Disadvantage
 By making the hardware simpler, RISC puts a
greater burden on the software.
 Software needs to become more complex.
 Software developers need to write more lines
for the same tasks.

Computer Organization & Architecture .24 Spring 2019

 Commercial Processors
 RISC
 DEC Alpha, AMD Am29000, ARC, ARM, Atmel AVR,
Blackfin, Intel i860 and i960, MIPS, Motorola 88000, PA-
RISC, PowerPC, RISC-V, SuperH, and SPARC.
 The use of ARM architecture processors in smart phones
and tablet computers such as the iPad and Android
devices provided a wide user base for RISC-based
systems.
 MIPS, PowerPC, SPARC, Itanium, ARM, Apple

 CISC
 Motorola 6800, 6809 and 68000-families; the Intel 8080
and x86-family; the Zilog Z80, Z8 and Z8000-families; the
Intel 8051-family.

Computer Organization & Architecture .25 Spring 2019

  RISC and CISC architectures are becoming more and more
alike.
 Many of today's RISC chips support just as many
instructions as yesterday's CISC chips.
 The PowerPC 601 (RISC), for example, supports more instructions
than the Pentium (CISC).
 Furthermore today's CISC chips use many techniques formerly
associated with RISC chips.

Computer Organization & Architecture .26 Spring 2019

Computer Organization & Architecture .27 Spring 2019
 Illustration through Example

Computer Organization & Architecture .28 Spring 2019

 CISC Approach
 Primary goal of CISC is to complete a task in as few lines of
assembly instruction as possible.
 This is achieved by building processor hardware that is
capable of understanding and executing a series of
operations.
 For this particular task, a CISC
 Processor would come prepared with a specific instruction (e.g.
"MULT").
 When executed, this instruction loads the two values into separate
registers, multiplies the operands in the execution unit, and then
stores the product in the appropriate register.
 Thus, the entire task of multiplying two numbers can be completed
with one instruction

Computer Organization & Architecture .29 Spring 2019

 CISC Instruction
 Define a “complex instruction”: MULT
 MULT: Load, multiply and store (operation valid for memory to
memory) & in multi clock cycles.
 MULT 2:3, 5:2

 Advantages:
 Compiler has to do very little work to translate a high-level
language statement into assembly.
 Because the length of the code is relatively short, very little RAM is
required to store instructions.

 Disadvantage: The emphasis is put on building complex

instructions directly into the complex hardware.

Computer Organization & Architecture .30 Spring 2019

 RISC Approach
 RISC processors only use simple instructions that can be
executed within one clock cycle.
 The "MULT" command described above could be divided
into three separate commands:
 "LOAD," which moves data from the memory bank to a register,
- LOAD A, 2:3
- LOAD B, 5:2
 "PROD," which finds the product of two operands located within
the registers, and
- PROD A, B
 "STORE," which moves data from a register to the memory banks.
- STORE 2:3, A

Computer Organization & Architecture .31 Spring 2019

  At first, this may seem like a much less efficient way of
completing the operation.
 Because there are more lines of code, more RAM is needed to store
the assembly level instructions.
 The compiler must also perform more work to convert a high-level
language statement into code of this form.

 However, the RISC strategy also brings some very

important advantages.
 Because each instruction requires only one clock cycle to execute,
the entire program will execute in approximately the same amount
of time as the multi-cycle "MULT“ command.
 These RISC "reduced instructions" require less transistors of
hardware space than the complex instructions, leaving more room
for general purpose registers.
 Because all of the instructions execute in a uniform amount of time
(i.e. one clock), pipelining is possible.
Computer Organization & Architecture .32 Spring 2019
  After a CISC-style "MULT" command is executed, the
processor automatically erases the registers (LESS SPACE).
 If one of the operands needs to be used for another computation,
the processor must re-load the data from the memory bank into a
register.

 In RISC, the operand will remain in the register until

another value is loaded in its place (MORE SPACE :
REGISTER)

Computer Organization & Architecture .33 Spring 2019

 The Performance Equation (Describing CISC & RISC )

 Equation :

 The CISC approach attempts to minimize the number of

instructions per program, sacrificing the number of cycles
per instruction.
 RISC does the opposite, reducing the cycles per instruction
at the cost of the number of instructions per program.

Computer Organization & Architecture .34 Spring 2019

 The Overall RISC Advantage

 The trend is highly supporting the idea of RISC.

 This is primarily due to advancements in other areas of
computer technology. The price of RAM has decreased
dramatically. In 1977, 1MB of DRAM cost about $5,000. By
1994, the same amount of memory cost only $6 (when
adjusted for inflation).
 Compiler technology has also become more sophisticated,
so that the RISC use of RAM and emphasis on software has
become ideal.

Computer Organization & Architecture .35 Spring 2019

 CISC vs RISC

The terms CISC and RISC have become less meaningful with the
continued evolution of both CISC and RISC designs and implementations
Computer Organization & Architecture .36 Spring 2019
 Below the Program
 High-level language program (in C)
swap (int v[], int k)
{int temp;
temp = v[k];
v[k] = v[k+1];
v[k+1] = temp;
}
C compiler
 Assembly language program (for MIPS)
swap: sll $2, $5, 2
add $2, $4,$2
lw $15, 0($2)
lw $16, 4($2)
sw $16, 0($2)
sw $15, 4($2)
jr $31 assembler

 Machine (object) code (for MIPS)

000000 00000 00101 0001000010000000
000000 00100 00010 0001000000100000
. . .
Computer Organization & Architecture .37 Spring 2019
 Levels of Representation
temp = v[k];
High Level Language
Program (e.g., C) v[k] = v[k+1];
v[k+1] = temp;
Compiler
Assembly Language lw $t0, 0($2)
lw $t1, 4($2)
Program (e.g.,MIPS) sw $t1, 0($2)
sw $t0, 4($2)
Assembler
Machine Language 0000 1001 1100 0110 1010 1111 0101 1000
Program (MIPS) 1010 1111 0101 1000 0000 1001 1100 0110
1100 0110 1010 1111 0101 1000 0000 1001
0101 1000 0000 1001 1100 0110 1010 1111
Machine
Interpretation
Hardware Architecture Description
(Verilog, VHDL)
Architecture
Implementation

Logic Circuit Description

(Xilinx ISE, Modelsim)

Computer Organization & Architecture .38 Spring 2019

 Hardware/Software Interface
 Instruction set architecture
includes everything programmers
need to know to make a binary
Application software program to work
 Instruction
System software
 Arithmetic and Logic Unit (ALU),
registers, etc

hardware

Instruction set architecture

(architecture)

Computer Organization & Architecture .39 Spring 2019

 The Instruction Set Architecture

software

instruction set architecture

hardware

The interface description separating the

software and hardware.

Computer Organization & Architecture .40 Spring 2019

 What are Abstractions?

Application (ex: browser)

Operating
Compiler System
COA
Software Assembler (Mac OSX)
Instruction Set
Hardware Processor Memory I/O system Architecture

Datapath & Control

Digital Design
Circuit Design
transistors

Computer Organization & Architecture .41 Spring 2019

 Computer Architecture - Definition

 Computer Architecture = ISA + MO

 Instruction Set Architecture

 What the executable can “see” as underlying hardware
 Logical View

 Machine Organization
 How the hardware implements ISA ?
 Physical View

Computer Organization & Architecture .42 Spring 2019

 Major Components of a Computer

Computer Organization & Architecture .43 Spring 2019

 Anatomy: 5 components of any Computer

Personal Computer

Computer Keyboard,
Processor
Mouse
Memory Devices
Disk
Control Input
(where (where
(“brain”) programs,
programs,
data data
Datapath live when live when
(“brawn”) Output not running)
running)
Display,
Printer

Computer Organization & Architecture .44 Spring 2019

 Input Device Inputs Object Code
000000 00000 00101 0001000010000000
000000 00100 00010 0001000000100000
100011 00010 01111 0000000000000000
100011 00010 10000 0000000000000100
101011 00010 10000 0000000000000000
101011 00010 01111 0000000000000100
000000 11111 00000 0000000000001000

Processor Devices

Control Input
Memory  Input devices
 Keyboard
Datapath Output  Mouse
 Network
 Joysticks, trackballs, etc

Input devices bring the object code and input data

from the outside world into computer.

Computer Organization & Architecture .45 Spring 2019

 Object Code Stored in Memory

Processor Memory
Devices
000000 00000 00101 0001000010000000
000000 00100 00010 0001000000100000
100011 00010 01111 0000000000000000
Control 100011 00010 10000 0000000000000100 Input
101011 00010 10000 0000000000000000
101011 00010 01111 0000000000000100
000000 11111 00000 0000000000001000
Datapath Output

Memory holds both INSTRUCTIONS and DATA and you can’t tell the
difference. They are both just 32 bit strings of zeros and ones.

Computer Organization & Architecture .46 Spring 2019

 Memory Unit: to store the program
 Primary storage: fast memory
 Programs must be stored in fast memory when they are being
executed
 The memory contains a large number of semiconductor storage
cells, each containing a bit
 The unit of memory access is a byte or a word, not a bit
 To provide easy access to any byte/word, a distinct address is
associated with each byte location
 The number of bits in each word is called word length of the
computer. That is also the length of instructions.
 RAM: random access memory. Access time to any location is
uniform
 Memory hierarchy: L-1 cache, L-2 cache, main memory

 Secondary storage
 Magnetic disks, tapes, optical disks

Computer Organization & Architecture .47 Spring 2019

 How to execute a program?

 Sequential execution

Fetch

Exec Decode

Computer Organization & Architecture .48 Spring 2019

 Instruction Fetch
 How do you know which instruction is next?
 PC (Program Counter)
 Where to store PC? (disk, memory, cache, register)
 How to update PC? (sequential, branch)

Computer Organization & Architecture .49 Spring 2019

 Processor Fetches an Instruction

Processor fetches an instruction from memory

PC

Processor Memory
Devices
000000 00000 00101 0001000010000000
000000 00100 00010 0001000000100000
100011 00010 01111 0000000000000000
Control 100011 00010 10000 0000000000000100 Input
101011 00010 10000 0000000000000000
101011 00010 01111 0000000000000100
000000 11111 00000 0000000000001000
Datapath Output

Computer Organization & Architecture .50 Spring 2019

 Control Decodes the Instruction

Control decodes the instruction to determine

what to execute

Processor Devices
Control
000000 00100 00010 0001000000100000
Memory Input
Datapath
Output

Computer Organization & Architecture .51 Spring 2019

 Datapath Executes the Instruction

Datapath executes the instruction as directed

by control

Processor Devices
Control
000000 00100 00010 0001000000100000
Memory Input
Datapath
contents Reg #4 ADD contents Reg #2
results put in Reg #2
Output

Computer Organization & Architecture .52 Spring 2019

 Processor Organization
 Control needs to have the
 Ability to input instructions from memory
 Logic and means to control instruction sequencing
 Logic and means to issue signals that control the way information
flows between datapath components
 Logic and means to control what operations the datapath’s
functional units perform

 Datapath needs to have the

 Components - functional units (e.g., adder) and storage locations
(e.g., register file) - needed to execute instructions
 Components interconnected so that the instructions can be
accomplished
 Ability to load data from and store data to memory

Computer Organization & Architecture .53 Spring 2019

 Output Data Stored in Memory

At program completion the data to be output

resides in memory

Processor Memory
Devices

Control Input

00000100010100000000000000000000
Datapath 00000000010011110000000000000100 Output
00000011111000000000000000001000

Computer Organization & Architecture .54 Spring 2019

 Output Device Outputs Data

Processor Devices

Control Input
Memory

Datapath Output

00000100010100000000000000000000
00000000010011110000000000000100
00000011111000000000000000001000

Computer Organization & Architecture .55 Spring 2019