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THE MEMORY SYSTEM However, during a write cycle, the control circuitry of the MM must
ensure that only the specified byte is altered. In this case, the higher-
order 30 bits can specify the word and the lower-order 2 bits can
BASIC CONCEPTS:
specify the byte within the word.
The maximum size of the Main Memory (MM) that can be
used in any computer is determined by its addressing scheme. For Memory Access Times: -
example, a 16-bit computer that generates 16-bit addresses is capable
It is a useful measure of the speed of the memory unit. It is the
of addressing upto 216 =64K memory locations. If a machine generates time that elapses between the initiation of an operation and the
32-bit addresses, it can access upto 232 = 4G memory locations. This completion of that operation (for example, the time between READ
number represents the size of address space of the computer. and MFC).
If the smallest addressable unit of information is a memory Memory Cycle Time :-
word, the machine is called word-addressable. If individual memory
bytes are assigned distinct addresses, the computer is called byte- It is an important measure of the memory system. It is the
addressable. Most of the commercial machines are byte- minimum time delay required between the initiations of two
addressable. For example in a byte-addressable 32-bit computer, successive memory operations (for example, the time between two
each memory word contains 4 bytes. A possible word-address successive READ operations). The cycle time is usually slightly longer
assignment would be: than the access time.

RANDOM ACCESS MEMORY (RAM)

Word Address Byte Address
A memory unit is called a Random Access Memory if any
0 0 1 2 3 location can be accessed for a READ or WRITE operation in some
4 4 5 6 7 fixed amount of time that is independent of the location’s
address. Main memory units are of this type. This distinguishes
8 8 9 10 11 them from serial or partly serial access storage devices such as
. ….. magnetic tapes and disks which are used as the secondary storage
device.
. …..
Cache Memory
. …..
The CPU of a computer can usually process instructions and
With the above structure a READ or WRITE may involve
data faster than they can be fetched from compatibly priced main
an entire memory word or it may involve only a byte. In the case of
memory unit. Thus the memory cycle time become the bottleneck in the
byte read, other bytes can also be read but ignored by the CPU.

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system. One way to reduce the memory access time is to use cache d between the MM and CPU. This transfer takes place over the processor
memory. This is a small and fast memory that is inserted between bus, which has k address lines (address bus), n data lines (data bus)
the larger, slower main memory and the CPU. This holds the currently and control lines like Read, Write, Memory Function completed
active segments of a program and its data. Because of the locality of (MFC), Bytes specifies etc (control bus). For a read operation, the
address references, the CPU can, most of the time, find the relevant CPU loads the address into MAR, set READ to 1 and sets other
information in the cache memory itself (cache hit) and infrequently control signals if required. The data from the MM is loaded into MDR
needs access to the main memory (cache miss) with suitable size of and MFC is set to 1. For a write operation, MAR, MDR are suitably
the cache memory, cache hit rates of over 90% are possible leading loaded by the CPU, write is set to 1 and other control signals are set
to a cost-effective increase in the performance of the system. suitably. The MM control circuitry loads the data into appropriate
locations and sets MFC to 1. This organization is shown in the
CPU-Main Memory Connection – A block schematic: - following block schematic
From the system standpoint, the Main Memory (MM) unit
can be viewed as a “block box”. Data transfer between CPU and INTERNAL ORGANIZATION OF SEMICONDUCTOR
MM takes place through the use of two CPU registers, usually called MEMORY CHIPS
MAR (Memory Address Register) and MDR (Memory Data Register). If
MAR is K bits long and MDR is ‘n’ bits long, then the MM unit may Memory chips are usually organized in the form of an array
contain upto 2k addressable locations and each location will be ‘n’ of cells, in which each cell is capable of storing one bit of information.
bits wide, while the word length is equal to ‘n’ bits. During a A row of cells constitutes a memory word, and the cells of a row are
“m connected to a common line referred to as the word line, and this line
e m is driven by the address decoder on the chip. The cells in each column
o ry are connected to a sense/write circuit by two lines known as bit lines.
cy The sense/write circuits are connected to the data input/output lines
c le” of the chip. During a READ operation, the Sense/Write circuits
, n sense, or read, the information stored in the cells selected by a word
bit line and transmit this information to the output lines. During a
s of write operation, they receive input information and store it in the cells
dat of the selected word.
a
ma The following figure shows such an organization of a memory chip
y be consisting of 16 words of 8 bits each, which is usually referred to as a
tra 16 x 8 organization.
n sfe
r re

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Another type of organization for 1k x 1 format is shown below:

The 10-bit address is divided into two groups of 5 bits each to form the
row and column addresses for the cell array. A row address selects a
row of 32 cells, all of which are accessed in parallel. One of these,
selected by the column address, is connected to the external data
lines by the input and output multiplexers. This structure can store
1024 bits, can be implemented in a 16-pin chip.

The data input and the data output of each Sense/Write circuit
are connected to a single bi-directional data line in order to reduce the
number of pins required. One control line, the R/W (Read/Write)
input is used a specify the required operation and another control
line, the CS (Chip Select) input is used to select a given chip in a
multichip memory system. This circuit requires 14 external
connections, and allowing 2 pins for power supply and ground
connections, can be manufactured in the form of a 16-pin chip. It can
store 16 x 8 = 128 bits.

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These transistors act as switches that can be opened or closed under

The common properties of Semiconductor memory. control of the word line. When the word line is at ground level, the
 All the Semiconductor memories like RAM & ROM are random transistors are turned off and the latch retains its state. For example, let us
access memories. assume that the cell is in state 1 if the X Bit lines logic value at point
 Semi conductor memories are bi-stable status like 1 or 0. X is 1 and at point Y is 0. This state is maintained as long as the signal on
the word line is at ground level.
 New data can be written rapidly into semi conductor memories.
 The existing data can be accessed randomly. Read Operation : In order to read the state of the SRAM cell, the word
 Semi-conductor memories organized in the manner of array. line is activated to close switches T1 and T2 .If the cell is in state 1, the
 The semi conductor memories are Volatile in nature. signal on the bit line b is high and the signal on the bit line b is low. The
opposite is true if the cell is in state 0. Thus b and b‟ are compliments of
Static Memories each other. Sense/Write circuits at the end of the bit lines monitor the state
of b and b and set the output accordingly.
Memories that consist of circuits capable of retaining their state as long
as power is applied are known as static memories. Write Operation : The state of the cell is set by placing the appropriate
value on bit line b and its complement b‟, and then activating the word
line. This forces the cell into the corresponding state. The required signals
on the bit lines are generated by the Sense/Write circuit.

CMOS Cell : A CMOS realization of the static RAM cell is given below:

The above figure illustrates how a static RAM (SRAM) cell may be
implemented. Two inverters are cross- connected to form a latch. The
latch is connected to two bit lines by transistors T1 and T2.

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Transistor pairs (T3, T5 ) and (T4 , T6) form the inverters in the latch (see
Appendix A).The state of the cell is read or written as just explained. For
example, in state 1, the voltage at point X is maintained high by having
transistors T3 and T6 on, while Tare off. Thus, if T1 and T2 are turned
on (closed), bit lines b and b‟ will have high and low signals, respectively.

Asynchronous DRAMS restoring the capacitor charge to its full value. An example of a dynamic
memory cell that consists of a capacitor, C, and a transistor, T, is shown
Information is stored in a dynamic memory cell in the form of a charge below:
on a capacitor, and this charge can be maintained for only tens of
milliseconds. Since the cell is required to store information for a much A sense amplifier connected to the bit line detects whether the
longer time, its contents must be periodically refreshed by charge stored on the capacitor is above the threshold. If so, it drives the bit
line to a full voltage that represents logic value 1. This voltage recharges
the capacitor to full charge that corresponds to logic value 1. If the sense
amplifier detects that the charge on the capacitor will have no charge,
representing logic value 0.

A 16-megabit DRAM chip, configured as 2M×8, is shown below.

 Each row can store 512 bytes. 12 bits to select a row, and 9 bits to
select a group in a row. Total of 21 bits.

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• First apply the row address; RAS signal latches the row address. Then
apply the column address, CAS signal latches the address.

 A Read operation causes the contents of all cells in the selected row to
be loaded into these latches.

 But, if an access is made for refreshing purpose only, it will not change
the contents of these latches; it will merely refresh the contents of the
cells.
• Timing of the memory unit is controlled by a specialized unit which  Data held in the latches that correspond to the selected column(s) are
generates RAS and CAS.• This is asynchronous DRAM transferred into the output register, thus becoming available on the data
output pins.
Synchronous DRAMs  SDRAMs have several different modes of operation, which can be
selected by writing control information into a mode register. For
In these DRAMs, operation is directly synchronized with a clock signal. example, burst operations of different lengths are specified.
The below given figure indicates the structure of an SDRAM.
 The output of each sense amplifier is connected to a latch.  The burst operations use the block transfer capability described
before as fast page mode feature.

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 The SDRAM automatically increments the column address to access

 In SDRAMs, it is not necessary to provide externally generated next three sets of the bits in the selected row, which are placed on the data
pulses on the CAS line to select successive columns. The necessary lines in the next clock cycles.
control signals are provided internally using a column counter and the

Double Data Rate- Synchronous DRAMs (DDR- SDRAMs)

To assist the processor in accessing data at high enough rate, the cell
array is organized in two banks. Each bank can be accessed separately.
Consecutive words of a given block are stored in different banks. Such
interleaving of words allows simultaneous access to two words that are
transferred on the successive edges of the clock. This type of SDRAM
is called Double Data Rate SDRAM (DDR- SDRAM).

Structure of larger memories

clock signal. New data can be placed on the data lines in each clock
cycles. All actions are triggered by the rising edge of the clock.
The figure shows the timing diagram for a burst read of length 4.

 First, the row address is latched under control of the RAS signal.

 Then, the column address latched under control of the CAS signal.

 After a delay of one clock cycle, the first set of data bits is placed on
the data lines.

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 Implementing a memory unit of 2M words of 32 bits each.  Packaging considerations have led to the development of larger
memory units known as SIMMs (Single In-line Memory Modules) and
 Using 512x8 static memory chips. Each column consists of 4 chips. DIMMs (Dual In-line Memory Modules).
Each chip implements
one byte position.  Memory modules are an assembly of memory chips on a small board
that plugs vertically onto a single socket on the motherboard.
 A chip is selected by setting its chip select control line to 1. Selected  Occupy less space on the motherboard.
chip places its data  Allows for easy expansion by replacement.
on the data output line, outputs of other chips are in high impedance state. Recall that in a dynamic memory chip, to reduce the number of pins,
multiplexed addresses are used.
 21 bits to address a 32-bit word. High order 2 bits are needed to select
the row, by activating the four Chip Select signals.  Address is divided into two parts:
 High-order address bits select a row in the array.
 19 bits are used to access specific byte locations inside the selected  They are provided first, and latched using RAS signal.
chip.  Low-order address bits select a column in the row.
 They are provided later, and latched using CAS signal.
 However, a processor issues all address bits at the same time.
 In order to achieve the multiplexing, memory controller circuit is
inserted between the processor and memory.

Dynamic Memory System Memory System Considerations

 Large dynamic memory systems can be implemented using DRAM  Recall that in a dynamic memory chip, to reduce the number of pins,
chips in a similar way to static memory systems. multiplexed
addresses are used.
 Placing large memory systems directly on the motherboard will occupy
a large amount of space.  Address is divided into two parts:
 High-order address bits select a row in the array.
 Also, this arrangement is inflexible since the memory system cannot be
expanded easily.  They are provided first, and latched using RAS signal.
 Low-order address bits select a column in the row.

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Refresh counter as the source and its contents are thus loaded into the row
 They are provided later, and latched using CAS signal. address latches of all memory chips when the RAS signal is activated.
However, a processor issues all address bits at the same time.
In order to achieve the multiplexing, memory controller circuit is inserted Semi-Conductor Rom Memories: -
between the processor and memory.
Semiconductor read-only memory (ROM) units are well suited as the
control store components in micro programmed processors and also as the
parts of the main memory that contain fixed programs or data. The
following figure shows a possible configuration for a bipolar ROM cell.
The word line is normally held at a low voltage. If a word is to be elected,
the voltage of the corresponding word line is momentarily raised, which
causes all transistors whose emitters are connected to their corresponding
bit lines to be turned on. The current that flows from the voltage supply to
the bit line can be detected by a sense circuit. The bit positions in which
current is detected are read as 1s, and the remaining bits are read as O.
.
Therefore, the contents of a given word are determined by the pattern of
emitter to bitline Connections similar configurations are possible in MOS
technology.

Refresh Operation

The Refresh control block periodically generates Refresh, requests,

causing the access control block to start a memory cycle in the normal
way. This block allows the refresh operation by activating the Refresh
Grant line. The access control block arbitrates between Memory Access
requests and Refresh requests, with priority to refresh requests
in the case of a tie to ensure the integrity of the stored data.
As soon as the Refresh control block receives the Refresh Grant signal, it
activates the Refresh line. This causes the address multiplexer to select the

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PROM issue. EPROM chips can be rewritten many times. Erasing an EPROM
: requires a special tool that emits a certain frequency of ultraviolet (UV)
Creating light. EPROMs are configured using an EPROM programmer that
ROM provides voltage at specified levels depending on the type of EPROM
chips used.
totally Once again we have a grid of columns and rows. In an EPROM, the cell at
from each intersection has two transistors. The two transistors are separated
scratch from each other by a thin oxide layer. One of the transistors is known as
is time-consuming and very expensive in small quantities. For this reason, the floating gate and the other as the control gate. The floating gate's only
mainly, developers created a type of ROM known as programmable read- link to the row (wordline) is through the control gate. As long as this link
only memory (PROM). Blank PROM chips can be bought inexpensively is in place, the cell has a value of 1. To change the value to 0 requires a
and coded by anyone with a special tool called a programmer. curious process called Fowler-Nordheim tunneling. Tunneling is used to
alter the placement of electrons in the floating gate. An electrical charge,
PROM chips have a grid of columns and rows just as ordinary ROMs do. usually 10 to 13 volts, is applied to the floating gate. The charge comes
The difference is that every intersection of a column and row in a PROM from the column (bitline), enters the floating gate and drains to a ground.
chip has a fuse connecting them. A charge sent through a column will passThis charge causes the floating-gate transistor to act like an electron gun.
through the fuse in a cell to a grounded row indicating a value of 1. Since
The excited electrons are pushed through and trapped on the other side of
all the cells have a fuse, the initial (blank) state of a PROM chip is all 1s.
the thin oxide layer, giving it a negative charge. These negatively charged
To change the value of a cell to 0, you use a programmer to send a electrons act as a barrier between the control gate and the floating gate. A
specific amount of current to the cell. The higher voltage breaks the device called a cell sensor monitors the level of the charge passing
connection between the column and row by burning out the fuse. This through the floating gate. If the flow through the gate is greater than 50
process is known as burning the PROM. percent of the charge, it has a value of 1. When the charge passing through
drops below the 50-percent threshold, the value changes to 0. A blank
PROMs can only be programmed once. They are more fragile than EPROM has all of the gates fully open, giving each cell a value of 1.
ROMs. A jolt of static electricity can easily cause fuses in the PROM to
burn out, changing essential bits from 1 to 0. But blank PROMs are To rewrite an EPROM, you must erase it first. To erase it, you must
inexpensive and are great for prototyping the data for a ROM before supply a level of energy strong enough to break through the negative
committing to the costly ROM fabrication process. electrons blocking the floating gate. In a standard EPROM, this is best
EPROM :Working with ROMs and PROMs can be a wasteful business. accomplished with UV light at a frequency of 253.7. Because this
Even though they are inexpensive per chip, the cost can add up over particular frequency will not penetrate most plastics or glasses, each
time. Erasable programmable read-only memory (EPROM) addresses this EPROM chip has a quartz window on top of it. The EPROM must be very
close to the eraser's light source, within an inch or two, to work properly.

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called blocks. Flash memory works much faster than traditional

An EPROM eraser is not selective, it will erase the entire EPROM. The EEPROMs because it writes data in chunks, usually 512 bytes in size,
EPROM must be removed from the device it is in and placed under the instead of 1 byte at a time.
UV light of the EPROM eraser for several minutes. An EPROM that is
left under too long can become over-erased. In such a case, the EPROM's
floating gates are charged to the point that they are unable to hold the Speed, Size and Cost
electrons at all.
A big challenge in the design of a computer system is to provide a
EEPROMs and Flash Memory :Though EPROMs are a big step up sufficiently large memory, with a reasonable speed at an affordable cost.
from PROMs in terms of reusability, they still require dedicated
equipment and a labor-intensive process to remove and reinstall them each
time a change is necessary. Also, changes cannot be made incrementally
to an EPROM; the whole chip must be erased. Electrically erasable
programmable read-only memory (EEPROM) chips remove the biggest
drawbacks of EPROMs.

 The chip does not have to removed to be rewritten.

 The entire chip does not have to be completely erased to change a
specific portion of it.
 Changing the contents does not require additional dedicated
equipment.

Instead of using UV light, you can return the electrons in the cells of an
EEPROM to normal with the localized application of an electric field to
each cell. This erases the targeted cells of the EEPROM, which can then
be rewritten. EEPROMs are changed 1 byte at a time, which makes them
versatile but slow. In fact, EEPROM chips are too slow to use in many Static RAM: Very fast, but expensive, because a basic SRAM cell has a
products that make quick changes to the data stored on the chip. complex circuit making it impossible to pack a large number of cells onto
a single chip.
Manufacturers responded to this limitation with Flash memory, a type of Dynamic RAM: Simpler basic cell circuit, hence are much less
EEPROM that uses in-circuit wiring to erase by applying an electrical expensive, but significantly slower than SRAMs.
field to the entire chip or to predetermined sections of the chip

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Magnetic disks: Storage provided by DRAMs is higher than SRAMs, but with slower semiconductor memory as the corresponding secondary
is still less than what is necessary. Secondary storage such as magnetic level. At a different point in the hierarchy, the same S.C memory
disks provides a large amount of storage, but is much slower than could be the primary level with disk as the secondary level.
DRAMs.

CACHE MEMORY:
Analysis of a large number of typical programs has shown that
most of their execution time is spent on a few main row lines in which a
number of instructions are executed repeatedly. These instructions may
constitute a simple loop, nested
loops or few procedure that
repeatedly call each other. The
main observation is that many
instructions in a few localized
are as of the program are
repeatedly executed and that
the remainder of the program
is accessed relatively
infrequently. This
phenomenon is referred to
as locality of reference.

If the active segments of a program can be placed in a fast memory, then

the total execution time can be significantly reduced, such a memory
is referred as a cache memory which is in served between the CPU and
the main memory as shown in fig.

Two Level memory Hierarchy: We will adopt the terms Primary

level for the smaller, faster memory and the secondary level for larger,
slower memory, we will also allow cache to be a primary level

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Difference between RAM & ROM

Basic for
RAM ROM
Comparison
Stands for Random Access Read Only Memory
Memory
Memory Type Volatile Non-volatile
Memory Capacity 1- 256 GB per chip 4-8 MB per Chip
Operation Type Read and Write both Read only
Speed Fast Comparatively slow
Storage type Temporary Permanent
Also referred as Primary Memory Secondary Memory
Presence of data The stored data in RAM Data retained in ROM
according to power lost in case of power even if the power is
source failure turned off.
Accessibility to Processor can directly Processor cannot
Processor access the data in RAM directly access the data
in ROM
Cost High Low
Types SRAM , DRAM PROM ,EPROM
Difference between DRAM & SRAM ,EEPROM

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