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    Instruction Sets: Computer Architecture Taxonomy. Assembly Language

    Uploaded by

    Lordwin Micheal

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    © All Rights Reserved
    Download as PPTX, PDF, TXT or read online from Scribd

    Instruction Sets: Computer Architecture Taxonomy. Assembly Language

    Uploaded by

    Lordwin Micheal
    51 views16 pages

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    Download as pptx, pdf, or txt
    51 views16 pages

    Instruction Sets: Computer Architecture Taxonomy. Assembly Language

    Uploaded by

    Lordwin Micheal

    Copyright:

    © All Rights Reserved
    Download as PPTX, PDF, TXT or read online from Scribd
    Download as pptx, pdf, or txt
    You are on page 1of 16

    Instruction sets

     Computer architecture taxonomy.


     Assembly language.

    Computers as Components 3e
    © 2012 Marilyn Wolf
    von Neumann architecture

     Memory holds data, instructions.


     Central processing unit (CPU) fetches
    instructions from memory.
     Separate CPU and memory distinguishes
    programmable computer.
     CPU registers help out: program counter
    (PC), instruction register (IR), general-
    purpose registers, etc.
    Computers as Components 3e
    © 2012 Marilyn Wolf
    CPU + memory

    address
    200
    PC
    memory data
    CPU
    200 ADD r5,r1,r3 ADD IR
    r5,r1,r3

    Computers as Components 3e
    © 2012 Marilyn Wolf
    Harvard architecture

    address
    data memory
    data PC
    CPU
    address

    program memory data

    Computers as Components 3e
    © 2012 Marilyn Wolf
    von Neumann vs. Harvard

     Harvard can’t use self-modifying code.


     Harvard allows two simultaneous memory
    fetches.
     Most DSPs use Harvard architecture for
    streaming data:
     greater memory bandwidth;
     more predictable bandwidth.

    Computers as Components 3e
    © 2012 Marilyn Wolf
    RISC vs. CISC

     Complex instruction set computer (CISC):


     many addressing modes;
     many operations.
     Reduced instruction set computer (RISC):
     load/store;
     pipelinable instructions.

    Computers as Components 3e
    © 2012 Marilyn Wolf
    Instruction set
    characteristics

     Fixed vs. variable length.


     Addressing modes.
     Number of operands.
     Types of operands.

    Computers as Components 3e
    © 2012 Marilyn Wolf
    Programming model

     Programming model: registers visible to


    the programmer.
     Some registers are not visible (IR).

    Computers as Components 3e
    © 2012 Marilyn Wolf
    Multiple implementations

     Successful architectures have several


    implementations:
     varying clock speeds;
     different bus widths;
     different cache sizes;
     etc.

    Computers as Components 3e
    © 2012 Marilyn Wolf
    Assembly language

     One-to-one with instructions (more or


    less).
     Basic features:
     One instruction per line.
     Labels provide names for addresses (usually
    in first column).
     Instructions often start in later columns.
     Columns run to end of line.
    Computers as Components 3e
    © 2012 Marilyn Wolf
    ARM assembly language
    example

    label1 ADR r4,c
    LDR r0,[r4] ; a comment
    ADR r4,d
    LDR r1,[r4]
    SUB r0,r0,r1 ; comment

    Computers as Components 3e
    © 2012 Marilyn Wolf
    Pseudo-ops

     Some assembler directives don’t


    correspond directly to instructions:
     Define current address.
     Reserve storage.
     Constants.

    Computers as Components 3e
    © 2012 Marilyn Wolf
    VLIW
     VLIW: very long instruction word.
     Performs several instructions simultaneously.
     Architecture usually restricts the combination of
    instructions that can be performed at once.
     Superscalar vs. VLIW:
     Superscalar runs standard code, determines parallel
    operations at run time.
     VLIW determines parallelism at compile time.
     Packet: a set of instructions to be executed in parallel.

    Computers as Components 3e
    © 2012 Marilyn Wolf
    Data and control
    dependencies

    bnz r3, foo


    add r0, r1, r2
    Foo: …

     r0 + r1 must be performed  Add will be executed


    before r2 + r3. only if bnz fails.
    Overheads forComponents
    Computers as Computers3eas
    Components
    © 2012 Marilyn Wolf
    Data dependencies and
    parallelism

     All three additions can be


    performed at the same time.

    Computers as Components 3e
    © 2012 Marilyn Wolf
    VLIW and embedded
    computing

     VLIW is more energy-efficient than


    superscalar.
     VLIW is widely used in signal processing.
     Multimedia processing.
     Processing multiple channels of signals.

    Computers as Components 3e
    © 2012 Marilyn Wolf

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