IR/Inductive Drop Introduction: Power Supply Voltage Drop

IR/Inductive Drop Introduction
• One component of every chip is the network of wires used to

distribute power from the input power pin(s) to the circuitry
inside. Since these wires have resistance and inductive
impedance, the voltage that gets to the internal circuitry is less
than that applied to the chip. If this voltage drop (often called the
IR drop) is too severe, the circuits will not get enough voltage
and can malfunction or not meet their timing specifications.
• A 5% voltage drop typically produces a 10 to 15% delay
Power supply
voltage drop
1 MICROPROCESSOR DESIGN
IR/Inductive Drop Issues
• Complexity of Power Distribution Due

– RLC Nature of the Interconnect
– Frequency of Operation near 1 GHz
– Powers of 100 W, Currents of 100 A, and VDD of 1.2 V
– Allowable Voltage Noise at 10% of (VDD – Gnd)
• Over-design Incorporates Decoupling Capacitors that Have a

Large Area Penalty
• Still Better Than Under-design Producing Non-Working Chips
IR Drop
• Voltage reduction on the signal lines due to high

resistance:
– Interconnects scaling effect
– Long and narrow lines increase the resistance of the interconnects
IR Drop
• IR portion of voltage drop is caused by current flowing through a

resistive network.
– IR drop affects power (IR drop) and ground (bounce).
– IR drop is local phenomenon that occurs when a number of gates in
close proximity switch at once, or when resistance at a specific
portion of the grid is larger than expected.
– IR drop is global phenomenon in which activity in one region of a
chip causes IR drop in other region.
– Symptoms of IR drop include non-functional chips (worst case),
chips that fail timing specification, or intermittent or vector-
dependent failures.
IR/Inductive Drop
• Inductive Portion of Voltage

Drop is Caused by Package
Pin Inductance – typically 1 to
2 nH.
• Wire Self-Inductance of About
.5 pH/micron Becoming
Important
• Ball-Grid Array Packaging
Allows Power to be Supplied
Directly to Most Regions of
the Chip and Has 0.1 nH per
Solder Bump
Inductive Portion of Voltage Drop is Becoming
Significant
• Consider a bump and via that produce .2nH of inductance on

both a VDD and a Ground Line. Drivers on the line will draw
around 25 mA over 100 ps time interval as shown.
• VL = 2 X L di/dt = 100mV
• This is About the Allowable Noise Margin
• Situation Far Worse with Wire Bond
IR/Inductive Drop
• Overall slow down of the design due to slow charging of the

devices.
• IR/Inductive Drop in the Signal Line adds to the Problem
IR/Inductive Drop Physical Model
• Combined Resistive and Inductive Effects in Power/Ground

System.
Simultaneous Switching Noise
• Switch of all the lines simultaneously (such as an address
bus that goes from all 1's to all 0's) can cause so-called
“ground-bounce”; the flip-side of IR Drop
Ground Bounce - A Closer Look
IR Drop and Ground Bounce Fixes
• It’s the result of

– Self-inductance of ground and power pins
– Resistance of the Lines
– Impedance-mismatch, or
– Combination of above.
• In order to maximize “power integrity” provide:
– Extra ground and power pins
– Good bypassing,
– Control the rate of rise/fall of the lines,
– Impedance-matching termination,
Decoupling Capacitance Design
• Used to Keep Power Supply within Noise Budget

• Decoupling Capacitors Are Large-Valued
Capacitors that Hold a Reservoir of Charge
Located Near the Power Pins and Any Large Driver
• Required Current for Switching is Provided by
Local Decap
• On-Chip Decoupling Capacitance Implemented
Using NMOS Transistor
On-Chip Decoupling Capacitance
Implemented Using NMOS Transistor
Reduce IR Drop by Path Alterations
Identification of IR Drop Regions
Power Grid Analysis
• Transistor-level analysis is done by modeling the transistors as current

sources (tap currents) connected directly to the power grid
– Tap current can be static or dynamic
– In order to perform static or dynamic type analysis
Analyzing IR Drop
Current passing through VDD

wire--in this case the power grid--
experiences some resistance
throughout the long routes in the
design.
Power Grid analysis models

transistors currents as current
sources attached (tap currents) to
the power grid
Modeling Current Sources and Sinks
Current at half-maximum
Physical View of Power Grid
Solving for the Supply Voltage and Current
Levels at Each Cell
Inclusion of Switching Information
(Dynamic vector simulation)

IR/Inductive Drop Introduction: Power Supply Voltage Drop

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IR/Inductive Drop Introduction

• One component of every chip is the network of wires used to

• Complexity of Power Distribution Due

• Over-design Incorporates Decoupling Capacitors that Have a

• Still Better Than Under-design Producing Non-Working Chips

• Voltage reduction on the signal lines due to high

– Long and narrow lines increase the resistance of the interconnects

• IR portion of voltage drop is caused by current flowing through a

• Inductive Portion of Voltage

• Consider a bump and via that produce .2nH of inductance on

• Overall slow down of the design due to slow charging of the

• Combined Resistive and Inductive Effects in Power/Ground

• It’s the result of

• Used to Keep Power Supply within Noise Budget

• Transistor-level analysis is done by modeling the transistors as current

Current passing through VDD

Power Grid analysis models

(Dynamic vector simulation)

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