PIT: Programmable Interval Timer: Introduction To 8253/8254

PIT: Programmable Interval
Timer
Introduction to 8253/8254
8253/54 Timer
Timer Description and Initialization
• PIT (programmable Interval Timer)
• The 8253 chip was used in the IBM PC.
• 8253 and 8254 have exactly the same pinout.
• 8254 is a superset of the 8253.
• Consists of 3 independent 16 bit programmable counters(timers) each capable of counting

in binary or BCD
Pin Diagram
Pin Description of
8253/54
A0, A1, and CS
• Inside the 8253/54 timer, there
are 3 counters.
• Each timer works independently
and programmed separately.
• Each counter is assigned an
individual port
address(40H,41H,42H).
• The control register common to
all 3 counters and has its own
port(43H).
CLK
• CLK is the input clock frequency, which can range between 0 and 2
MHz for the 8253.
OUT
• Can have square-wave, one-shot, and other square-shape waves for
various duty cycles but no sine-wave or saw-tooth shapes.
Gate
• This pin is used to enable or disable the counter.
D0-D7
• The D0-D7 data bus of the 8253/54 is a bidirectional bus
connected to D0-D7 of the system data bus.
• RD and WR are connected to IOR and IOW control signals of the
system bus.
Initialization of the 8253/54
• Each of the three counters of the 8253/54 must be programmed
separately.
• The 8253/54 must be initialized before it is used.
There are 6 Operation Modes
Mode 0 Interrupt on terminal count
Mode 1 Programmable one-shot
Mode 2 Rate Generator
Mode 3 Square wave rate generator
Mode 4 Software triggered strobe
Mode 5 Hardware trigger strobe
Using counter 0
• The wave shape is a square wave.

• D0 = 0 for the binary value.
• D3 D2 D1 = 011, mode 3
• D4 D5 = 11, for reading/writing the LSB first,
followed by MSB.
• D7 D6 = 00, for counter 0.
Read Operations
It is often desirable to read the Value of a counter without disturbing the count in progress.It can be done
in 3 ways.
(i)Simple read operation
(ii)Counter Latch Command
(iii)Read Back Command – It allows to check the count value, programmed mode, current status of the
OUT pin and Null Count flag of the selected counter(s). The Control word register has the following
format:
D7,D6 11
D5 COUNT: 0 Latches count of selected counter
D4 STATUS: 0 Latches status of selected counter
D3 D2 Selected counter
D1
D0 0
The command applies to the counter selected by D3,D2, D1.
The Read Back Command is completed by CPU reading. The

format of the byte read is as follows:
D7 OUTPUT. Gives the value of the corresponding OUT pin.
D6 NULL COUNT. 0 means count is available for reading.
D5 – Same meaning as the bits in the control word for the indicated counter.
D0
Mode 0: interrupt on terminal count
The output in this mode is initially low, and will remain

low for the duration of the count if GATE = 1.
Width of low pulse = NT
Where N is the the clock count loaded into counter, and T
is the clock period of the CLK input.
Mode 0: interrupt on terminal
count
When the terminal count is reached, the output will go high

and remain high until a new control word or new count
number is loaded.
• In this mode, if GATE input becomes low at the middle of
the count, the count will stop and the output will be low.
• The count resumes when the gate becomes high again.
• This in effect adds to the total time the output is low.
Mode 1: programmable one-
shot
• This mode is also called hardware triggerable one-shot.
• The triggering must be done through the GATE input by sending a
0-to-1 pulse to it.
• The following two steps must be performed:
1. Load the count registers.
2. A 0-to-1 pulse must be sent to the GATE input to trigger the counter.
• Contrast this with mode 0, in which the counter produces the output
immediately after the counter is loaded as long as GATE = 1.
• In mode 1 after sending the 0-to-1 pulse to GATE, OUT becomes
low and stays low for a duration of NT, then becomes high and
stays high until the gate is triggered again.
Mode 2: rate generator
Mode 2 is also called divide-by-N counter.
• In this mode, if GATE = 1, OUT will be high for the NT clock period,
goes low for only one clock pulse, then the count is reloaded
automatically, and the process continues indefinitely.
Mode 3: square wave rate
generator
In this mode if GATE = 1, OUT is a square wave where the high pulse is
equal to the low pulse if N is an even number.
• In this case the high part and low part of the pulse have the same
duration and are equal to (N/2)T (50% duty cycle)
• If N is an odd number, the high pulse is one clock pulse longer.
• This mode is widely used as a frequency divider and audio-tone
generator.
Mode 4: software trigger
strobe
•In this mode if GATE = 1, the output will go high upon loading the
count.
• It will stay high for the duration of NT.
• After the count reaches zero (terminal count), it becomes low for one
clock pulse, then goes high again and stays high until a new command
word or new count is loaded.
• To repeat the strobe, the count must be reloaded again.
• Mode 4 is similar to mode 2, except that the counter is not reloaded
automatically.
• In this mode, the count starts the moment the count is written into the
counter.
Mode 5: hardware trigger
strobe
• This mode is similar to mode 4 except that the trigger must be done
with the GATE input.
• In this mode after the count is loaded, we must send a low-to-high
pulse to the gate to start the counter.

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PIT: Programmable Interval

• 8254 is a superset of the 8253.

• Consists of 3 independent 16 bit programmable counters(timers) each capable of counting

• The wave shape is a square wave.

The Read Back Command is completed by CPU reading. The

D7 OUTPUT. Gives the value of the corresponding OUT pin.

D6 NULL COUNT. 0 means count is available for reading.

The output in this mode is initially low, and will remain

When the terminal count is reached, the output will go high

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