Cache Memory

Computer Architecture
Cache memory
Dr. Danish Mahmood

Cache memory
• Computer Memory System Overview Location
• Characteristics of Memory Systems Capacity
• The Memory Hierarchy Registers Access method
• Cache Memory Principles L1 Cache Performance
• Elements of Cache Design L2 Cache Physical type
Main memory Physical characteristics
• Cache Addresses
Disk cache Organisation
• Cache Size
Disk
• Mapping Function
Optical
• Replacement Algorithms Tape
• Write Policy
• Line Size
• Number of Caches
• Pentium 4 Cache Organization
Characteristics CPU
Internal
External
• Location
Word size
• Capacity The natural unit of organisation
Number of words or Bytes
• Unit of transfer
• Access method Internal
• Performance Usually governed by data bus width
External
• Physical type Usually a block which is much larger than a word
Addressable unit
• Physical characteristics Smallest location which can be uniquely addressed
• Organisation
Capacity
• An obvious characteristic of memory is its capacity.
• For internal memory, this is typically expressed in terms of bits (1
byte 8 bits) or words.
• Common word lengths are 8, 16, and 32 bits.
• External memory capacity is typically expressed in terms of bytes.
Memory Accessing Methods
• Another distinction among memory types is the method of accessing
units of data. These include the following:
• Sequential
• Direct
• Random
• Associative
Sequential
• Memory is organized into units of data, called records.
• Access must be made in a specific linear sequence.
• Stored addressing information is used to separate records and assist
in the retrieval process.
• A shared read–write mechanism is used.
• Thus, the time to access an arbitrary record is highly variable.
• Tape units, are sequential access.
Direct access
• As with sequential access, direct access involves a shared read–write
mechanism.
• However, individual blocks or records have a unique address based on
physical location.
• Access is accomplished by
• direct access to reach a general vicinity plus sequential searching, counting, or
waiting to reach the final location.
• Again, access time is variable. Disk units, are direct access.
Random access
• Each addressable location in memory has a unique, physically wired-
in addressing mechanism.
• The time to access a given location is independent of the sequence of
prior accesses and is constant.
• Thus, any location can be selected at random and directly addressed
and accessed.
• Main memory and some cache systems are random access.
Associative
• This is a random access type of memory that enables one to make a
comparison of desired bit locations within a word for a specified
match.
• Thus, a word is retrieved based on a portion of its contents rather
than its address.
• As with ordinary random-access memory, each location has its own
addressing mechanism,
• and retrieval time is constant independent of location or prior access
patterns.
• Cache memories may employ associative access.
Performance
• From a user’s point of view, the two most important characteristics of
memory are
• capacity and performance.
• Three performance parameters are used:
• Access time
• Time between presenting the address and getting the valid data
• Memory Cycle time
• Time may be required for the memory to “recover” before next access
• Cycle time is access + recovery
• Transfer Rate
• Rate at which data can be moved
Cache-
Physical Types, Characteristics and organization
Physical Types Physical Organization
• Semiconductor Characteristics • Physical arrangement of
• RAM • Decay bits into words
• Magnetic • Volatility • Not always obvious
• Disk & Tape • Erasable • e.g. interleaved
• Optical • Power consumption
• CD & DVD
• Others
Difference between volatile and non volatile memory

The Memory Hierarchy
• The design constraints on a computer’s memory can be summed up
by three questions:
• How much? How fast? How expensive?
• There is a trade-off among the three key characteristics of memory:
• capacity, access time, and cost
• Across this spectrum of technologies, the following relationships hold:
• • Faster access time, greater cost per bit
• • Greater capacity, smaller cost per bit
• • Greater capacity, slower access time
The memory hierarchy
• As one goes down the hierarchy, the following occur:
a. Decreasing cost per bit
b. Increasing capacity
c. Increasing access time
d. Decreasing frequency of access of the memory by the processor
smaller, more expensive, faster memories are supplemented by larger,
cheaper, slower memories.
Basic terminologies
• This leads us to some definitions.
• A hit is when data is found at a given memory level.
• A miss is when it is not found.
• The hit rate is the percentage of time data is found at a given
memory level.
• The miss rate is the percentage of time it is not.
• Miss rate = 1 - hit rate.
• The hit time is the time required to access data at a given memory
level.
• The miss penalty is the time required to process a miss, including
the time that it takes to replace a block of memory plus the time it
takes to deliver the data to the processor.
Cache Memory Principles
There is a relatively large and slow

main memory together with a smaller,
faster cache memory. The cache
contains a copy of portions of main
memory.
Home work
• Please explain the term “Locality of Reference”.
• What is virtual memory and virtual address? Why and where it is
utilized in computer architecture.
Comparison of Cache Sizes
Processor Type
Year of
L1 cache L2 cache L3 cache
Introduction
IBM 360/85 Mainframe 1968 16 to 32 KB — —
PDP-11/70 Minicomputer 1975 1 KB — —
VAX 11/780 Minicomputer 1978 16 KB — —
IBM 3033 Mainframe 1978 64 KB — —
IBM 3090 Mainframe 1985 128 to 256 KB — —
Intel 80486 PC 1989 8 KB — —
Pentium PC 1993 8 KB/8 KB 256 to 512 KB —
PowerPC 601 PC 1993 32 KB — —
PowerPC 620 PC 1996 32 KB/32 KB — —
PowerPC G4 PC/server 1999 32 KB/32 KB 256 KB to 1 MB 2 MB
IBM S/390 G4 Mainframe 1997 32 KB 256 KB 2 MB
IBM S/390 G6 Mainframe 1999 256 KB 8 MB —
Pentium 4 PC/server 2000 8 KB/8 KB 256 KB —
High-end server/
IBM SP 2000 64 KB/32 KB 8 MB —
supercomputer
CRAY MTAb Supercomputer 2000 8 KB 2 MB —
Itanium PC/server 2001 16 KB/16 KB 96 KB 4 MB
SGI Origin 2001 High-end server 2001 32 KB/32 KB 4 MB —
Itanium 2 PC/server 2002 32 KB 256 KB 6 MB
IBM POWER5 High-end server 2003 64 KB 1.9 MB 36 MB
CRAY XD-1 Supercomputer 2004 64 KB/64 KB 1MB —
Cache/Main Memory Structure • If memory contains 2n
addressable words
– Memory can be broken up
into blocks with K words
per block. Number of
blocks = 2n / K
– Cache consists of C lines or
slots, each consisting of K
words
– How to map blocks of
memory to lines in the
cache?
In referring to the basic unit of the cache, the term line is used,
rather than the term block, for two reasons:
(1) to avoid confusion with a main memory block, which contains the
same number of data words as a cache line; and
(2) because a cache line includes not only K words of data, just as a
main memory block, but also include tag and control bits
Cache Read Operation - Flowchart
Typical Cache Organization

Cache Memory

Uploaded by

Copyright:

Available Formats

Cache Memory

Uploaded by

Document Information

Original Description:

Original Title

Copyright

Available Formats

Share this document

Share or Embed Document

Sharing Options

Did you find this document useful?

Is this content inappropriate?

Copyright:

Available Formats

Cache Memory

Uploaded by

Copyright:

Available Formats

Computer Architecture

Dr. Danish Mahmood

Difference between volatile and non volatile memory

There is a relatively large and slow

You might also like