COMPUTER ORGANIZATION AND DESIGN 5th

Edition
The Hardware/Software Interface

Chapter 2
Instructions: Language
of the Computer
Instruction set
 Set of instructions that a processor can
understand

Chapter 2 — Instructions: Language of the Computer — 2

Instruction Set Architecture

 Instruction Set Architecture is the structure

of a computer that a machine language
programmer (or a compiler) must
understand to write a correct (timing
independent) program for that machine

Chapter 2 — Instructions: Language of the Computer — 3

What ISA Defines

 Operations that the processor can execute

 Size of instructions (either fixed or variable)
 How to access data (addressing modes)
 Data Transfer mechanisms + how to access data
(lw, sw)
 Location of operands (either register or
memory)
 Control Mechanisms (branch, jump, etc)

Chapter 2 — Instructions: Language of the Computer — 4

A good ISA
 Portable, Compatible
 Lasts through many implementations
 Used in many different ways
 PMDs, Desktops, Servers, Tablets
 Provides convenient functionality to higher
layers
 Permits efficient implementation at lower
layers

Chapter 2 — Instructions: Language of the Computer — 5

ISA – Seven dimensions
 1) Class of ISA:
 Defined based on how memory is
accessed
 Almost all ISAs are general-purpose
register architectures
 Operands are registers or memory
locations

Chapter 2 — Instructions: Language of the Computer — 6

ISA – Seven dimensions
 Two main types
 Register-Memory ISAs
 Can access memory as part of many
instructions
 Example: 80x86 ISA
 Load-Store ISAs
 Can access memory only with load or store
instructions o Example: ARM, MIPS
 All recent ISAs are load-store class

Chapter 2 — Instructions: Language of the Computer — 7

ISA – Seven dimensions
 ② Memory Addressing:
 Virtually all computers use byte addressing to
access memory operands
 Some architectures, like ARM and MIPS, require
that the data must be aligned
 Data alignment means putting the data at a memory
address equal to some multiple of the word size
 A computer reads/ writes to a memory address in
word sized chunks
 Example: With word size of 4 bytes, the data to be
read should be at a memory address which is some
multiple of 4
Chapter 2 — Instructions: Language of the Computer — 8
ISA – Seven dimensions
 ③ Addressing Modes:
 Define how machine language instructions
in the architecture identify the operand(s)
of each instruction
 Specifies how to calculate the effective
memory address of an operand by using
information held in registers and/or
constants contained within a machine
instruction

Chapter 2 — Instructions: Language of the Computer — 9

ISA – Seven dimensions
 ④ Types & Sizes of Operands:
 Most ISAs like 80x86, ARM, and MIPS
support following operand types and sizes
 8-bit (ASCII character)
 16-bit (uni code character)
 32-bit (integer or word)
 64-bit (double word or long integer)
 Floating point 32-bit (single precision)
 64-bit (double precision)

Chapter 2 — Instructions: Language of the Computer — 10

ISA – Seven dimensions
 ⑤ Operations:
 Almost all ISAs support general category
of operations such as:
 Data transfer operations
 Arithmetic operations
 Logical operations
 Control operations
 Floating point operations

Chapter 2 — Instructions: Language of the Computer — 11

ISA – Seven dimensions
 ⑥ Control-flow Instructions:
 All ISAs support control-flow instructions
such as
 Conditional branches
 Unconditional jumps
 Procedure calls and returns

Chapter 2 — Instructions: Language of the Computer — 12

ISA – Seven dimensions
 ⑦ Encoding an ISA:
 Refers to the way a particular ISA formats its
instructions
 Two basic types
 Fixed Length: ARM and MIPS instructions are
fixed length , 32-bit long, simple to
encode/decode
 Variable Length: 80x86 encoding is variable
length, ranging from 1 to 18 bytes.
 Variable- length instructions can take less space than
fixed-length instructions, not easy to decode.
Chapter 2 — Instructions: Language of the Computer — 13
RISC Architecture
 Define RISC: Reduced Instruction Set Computer
 A type of microprocessor architecture that
utilizes a small, highly-optimized set of
instructions, rather than a more specialized set
of instructions often found in other types of
architectures
 First RISC projects came from IBM, Stanford, and
UCBerkeley in the late 70s
 Prof. John Hennessy, Stanford Univ., was the first to
propose MIPS architecture (an early stage RISC)

Chapter 2 — Instructions: Language of the Computer — 14

RISC Architecture
 Characteristic Design Features of RISC?
 One cycle execution time:
 RISC processors have a CPI (clock per instruction) of
one cycle.
 Great speed
 Easy
 Large number of registers: RISC design philosophy
generally incorporates a larger number of registers to
prevent in large amounts of interactions with memory

Chapter 2 — Instructions: Language of the Computer — 15

RISC VS CISC
 Main Features of CISC
 CISC attempts to make machine language
instructions similar to HLL statements
 A large number of instructions (> 200) with
complex instructions and data types
 Many and complex addressing modes
 Memory bottleneck is a major problem
 Due to complex addressing modes and multiple
memory accesses instruction

Chapter 2 — Instructions: Language of the Computer — 16

Problems with CISC
 Large instruction set requires complex and
time consuming hardware steps to decode
and execute instructions
 Instruction may take multiple clock cycles
to execute

Chapter 2 — Instructions: Language of the Computer — 17

RISC VS CISC

Chapter 2 — Instructions: Language of the Computer — 18

RISC VS CISC

Chapter 2 — Instructions: Language of the Computer — 19

RISC VS CISC

Chapter 2 — Instructions: Language of the Computer — 20

The MIPS Instruction Set

 Stanford MIPS commercialized by MIPS

Technologies
 Large share of embedded core market
 Applications in consumer electronics, network/storage
equipment, cameras, printers, …
 Typical of many modern ISAs
 Performs one operation at a time

Chapter 2 — Instructions: Language of the Computer — 21

Elements of an Instruction
 Operation code (Op code)
 Do this
 Source Operand reference
 To this
 Result Operand reference
 Put the answer here
 Next Instruction Reference
 When you have done that, do this...

Chapter 2 — Instructions: Language of the Computer — 22

Instruction cycle state
diagram

Chapter 2 — Instructions: Language of the Computer — 23

 §2.2 Operations of the Computer Hardware
Arithmetic Operations
 Add and subtract, three operands
 Two sources and one destination
add a, b, c # a gets b + c
 All arithmetic operations have this form

Chapter 2 — Instructions: Language of the Computer — 24

Compiling two C Assignment
Statements
 A= b + c ;
 D=a–e;
 Translation from C to MIPS assembly
language is performed by compiler
 Add a, b, c
 Sub d, a, e

Chapter 2 — Instructions: Language of the Computer — 25

Arithmetic Example
 C code:
f = (g + h) - (i + j);

 Compiled MIPS code:

add t0, g, h # temp t0 = g + h
add t1, i, j # temp t1 = i + j
sub f, t0, t1 # f = t0 - t1

Chapter 2 — Instructions: Language of the Computer — 26

Check yourself
 For a given function, which programming
language likely takes the most lines of
code?
 1. Java
 2. C
 3. MIPS assembly language

Chapter 2 — Instructions: Language of the Computer — 27

 §2.3 Operands of the Computer Hardware
Register Operands
 Arithmetic instructions use register
operands
 MIPS has a 32 × 32-bit register file
 Use for frequently accessed data
 Numbered 0 to 31
 32-bit data called a “word”
 Assembler names
 $t0, $t1, …, $t9 for temporary values
 $s0, $s1, …, $s7 for saved variables

Chapter 2 — Instructions: Language of the Computer — 28

MIPS Registers

Chapter 2 — Instructions: Language of the Computer — 29

Register Operand Example
 C code:
f = (g + h) - (i + j);
 f, …, j in $s0, …, $s4

 Compiled MIPS code:

add $t0, $s1, $s2
add $t1, $s3, $s4
sub $s0, $t0, $t1

Chapter 2 — Instructions: Language of the Computer — 30

Memory Operands
 Main memory used for composite data
 Arrays, structures, dynamic data
 Instructions that transfer data btw memory and
registers are called data transfer instructions
 To apply arithmetic operations
 Load values from memory into registers
 Store result from register to memory
 Memory is byte addressed
 Each address identifies an 8-bit byte
 Words are aligned in memory
 Address must be a multiple of 4

Chapter 2 — Instructions: Language of the Computer — 31

Memory Operand Example 1
 C code:
g = h + A[8];
 g in $s1, h in $s2, base address of A in $s3

 Compiled MIPS code:

 Index 8 requires offset of 32
 4 bytes per word
lw $t0, 32($s3) # load word
add $s1, $s2, $t0
offset base register

Chapter 2 — Instructions: Language of the Computer — 32

Memory Operand Example 2
 C code:
A[12] = h + A[8];
 h in $s2, base address of A in $s3

 Compiled MIPS code:

 Index 8 requires offset of 32
lw $t0, 32($s3) # load word
add $t0, $s2, $t0
sw $t0, 48($s3) # store word

Chapter 2 — Instructions: Language of the Computer — 33

Quiz
 Write the following sequence of code into
MIPS assembler:
 x = x + y + z - q;
 B[3] = x + y + z – B[7];
 Assume that x, y, z, q, B are stored in
registers $s1-$s5

Chapter 2 — Instructions: Language of the Computer — 34

Registers vs. Memory
 Registers are faster to access than
memory
 Operating on memory data requires loads
and stores
 More instructions to be executed
 Compiler must use registers for variables
as much as possible
 Only spill to memory for less frequently used
variables
 Register optimization is important!

Chapter 2 — Instructions: Language of the Computer — 35

Immediate Operands
 Constant data specified in an instruction
addi $s3, $s3, 4
 No subtract immediate instruction
 Just use a negative constant
addi $s2, $s1, -1

 Small constants are common

 Immediate operand avoids a load instruction

Chapter 2 — Instructions: Language of the Computer — 36

The Constant Zero
 MIPS register 0 ($zero) is the constant 0

 Useful for common operations

 E.g., move between registers
add $t2, $s1, $zero

Chapter 2 — Instructions: Language of the Computer — 37

 §2.5 Representing Instructions in the Computer
Representing Instructions
 Instructions are encoded in binary
 Called machine code
 MIPS instructions
 Encoded as 32-bit instruction words
 Small number of formats encoding operation code
(opcode), register numbers, …
 Register numbers
 $t0 – $t7 are reg’s 8 – 15
 $t8 – $t9 are reg’s 24 – 25
 $s0 – $s7 are reg’s 16 – 23

Chapter 2 — Instructions: Language of the Computer — 38

MIPS R-format Instructions
op rs rt rd shamt funct
6 bits 5 bits 5 bits 5 bits 5 bits 6 bits

 Instruction fields
 op: operation code (opcode)
 rs: first source register number
 rt: second source register number
 rd: destination register number
 shamt: shift amount (00000 for now)
 funct: function code (extends opcode)

Chapter 2 — Instructions: Language of the Computer — 39

R-format Example
op rs rt rd shamt funct
6 bits 5 bits 5 bits 5 bits 5 bits 6 bits

add $t0, $s1, $s2

special $s1 $s2 $t0 0 add

0 17 18 8 0 32

000000 10001 10010 01000 00000 100000

000000100011001001000000001000002

Chapter 2 — Instructions: Language of the Computer — 40

MIPS I-format Instructions
op rs rt constant or address
6 bits 5 bits 5 bits 16 bits

 Immediate arithmetic and load/store instructions

 rs, rt: source and target register number
 Constant: –215 to +215 – 1
 Address: offset added to base address in rs

Chapter 2 — Instructions: Language of the Computer — 41

Chapter 2 — Instructions: Language of the Computer — 42
Lw: rt field specifies the destination register

Chapter 2 — Instructions: Language of the Computer — 43

Quiz
 In the snippet of MIPS assembler code
below, how many times is instruction
memory accessed? How many times is
data memory accessed? (Count only
accesses to memory, not registers.)
 lw $v1, 0($a0)
 addi $v0, $v0, 1
 sw $v1, 0($a1)
 addi $a0, $a0, 1
Chapter 2 — Instructions: Language of the Computer — 44
 §2.6 Logical Operations
Logical Operations
 Instructions for bitwise manipulation
Operation C Java MIPS
Shift left << << sll
Shift right >> >>> srl
Bitwise AND & & and, andi
Bitwise OR | | or, ori
Bitwise NOT ~ ~ nor

 Useful for extracting and inserting

groups of bits in a word
Chapter 2 — Instructions: Language of the Computer — 45
Shift Operations
op rs rt rd shamt funct
6 bits 5 bits 5 bits 5 bits 5 bits 6 bits

 shamt: how many positions to shift

 Shift left logical
 Shift left and fill with 0 bits
 sll by i bits multiplies by 2i
 Shift right logical
 Shift right and fill with 0 bits
 srl by i bits divides by 2i (unsigned only)

Chapter 2 — Instructions: Language of the Computer — 46

Chapter 2 — Instructions: Language of the Computer — 47
Chapter 2 — Instructions: Language of the Computer — 48
Chapter 2 — Instructions: Language of the Computer — 49
AND Operations
 Useful to mask bits in a word
 Select some bits, clear others to 0
and $t0, $t1, $t2

$t2 0000 0000 0000 0000 0000 1101 1100 0000

$t1 0000 0000 0000 0000 0011 1100 0000 0000

$t0 0000 0000 0000 0000 0000 1100 0000 0000

Chapter 2 — Instructions: Language of the Computer — 50

Chapter 2 — Instructions: Language of the Computer — 51
OR Operations
 Useful to include bits in a word
 Set some bits to 1, leave others unchanged
or $t0, $t1, $t2

$t2 0000 0000 0000 0000 0000 1101 1100 0000

$t1 0000 0000 0000 0000 0011 1100 0000 0000

$t0 0000 0000 0000 0000 0011 1101 1100 0000

Chapter 2 — Instructions: Language of the Computer — 52

NOT Operations
 Useful to invert bits in a word
 Change 0 to 1, and 1 to 0
 MIPS has NOR 3-operand instruction
 a NOR b == NOT ( a OR b )
nor $t0, $t1, $zero Register 0: always
read as zero

$t1 0000 0000 0000 0000 0011 1100 0000 0000

$t0 1111 1111 1111 1111 1100 0011 1111 1111

Chapter 2 — Instructions: Language of the Computer — 53

 §2.7 Instructions for Making Decisions
Conditional Operations
 Branch to a labeled instruction if a
condition is true
 Otherwise, continue sequentially
 beq rs, rt, L1
 if (rs == rt) branch to instruction labeled L1;
 bne rs, rt, L1
 if (rs != rt) branch to instruction labeled L1;
 j L1
 unconditional jump to instruction labeled L1

Chapter 2 — Instructions: Language of the Computer — 54

Compiling If Statements
 C code:
if (i==j) f = g+h;
else f = g-h;
 f, g, … in $s0, $s1, …
 Compiled MIPS code:
bne $s3, $s4, Else
add $s0, $s1, $s2
j Exit
Else: sub $s0, $s1, $s2
Exit: …
Assembler calculates addresses

Chapter 2 — Instructions: Language of the Computer — 55

Quiz

Chapter 2 — Instructions: Language of the Computer — 56