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    Full Subtractor - Digital Analysis

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    Goutham Krish
    The document discusses the design of a full subtractor circuit. It includes the problem statement, descriptions of logic gates, a full subtractor, truth table, K-maps, boolean expressions, circuit diagram, input/output waveforms and delay analysis.

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    Full Subtractor - Digital Analysis

    Uploaded by

    Goutham Krish
    541 views15 pages
    The document discusses the design of a full subtractor circuit. It includes the problem statement, descriptions of logic gates, a full subtractor, truth table, K-maps, boolean expressions, circuit diagram, input/output waveforms and delay analysis.

    Original Description:

    It contains Truth Table, K maps, Circuit.

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    The document discusses the design of a full subtractor circuit. It includes the problem statement, descriptions of logic gates, a full subtractor, truth table, K-maps, boolean expressions, circuit diagram, input/output waveforms and delay analysis.

    Copyright:

    © All Rights Reserved
    Download as PPTX, PDF, TXT or read online from Scribd
    Download as pptx, pdf, or txt
    541 views15 pages

    Full Subtractor - Digital Analysis

    Uploaded by

    Goutham Krish
    The document discusses the design of a full subtractor circuit. It includes the problem statement, descriptions of logic gates, a full subtractor, truth table, K-maps, boolean expressions, circuit diagram, input/output waveforms and delay analysis.

    Copyright:

    © All Rights Reserved
    Download as PPTX, PDF, TXT or read online from Scribd
    Download as pptx, pdf, or txt
    of 15

    RAGHU ENGINEERING COLLEGE

    DEPARTMENT OF
    ELECTRONICS AND COMMUNICATION ENGINEERING
    Case study on
    DIGITAL ELECTRONICS

    PRESENTED BY:
    UNDER THE GUIDANCE OF T.V.PREETAM RAJ (18981A04H3)
    MR P.RAJESH T. GOUTHAM KRISHNA (18981A04H4)
    T. POOJA SHARMILA (18981A04H5)
    T.AMITH RAJ (18981A04H6)
    P.VIVEK (19985A0434)
    CONTENTS:
    1. PROBLEM
    2. ABOUT LOGIC GATES
    3. FULL SUBTRACTOR
    4. SOLUTION TO THE PROBLEM
    a) TRUTH TABLE
    b) K-MAPS
    c) BOOLEAN ALGEBRA
    d) CIRCUIT DIAGRAM
    e) INPUT /OUPUT WAVE FORMS
    5. DELAY ANALYSIS
    6. CONCLUSION
    7. REFERENCES
    PROBLEM:

    DESIGN THE CIRCUIT FOR FULL SUBTRACTOR AND DO DELAY


    ANALYSIS IN ALL POSSIBLE REALIZATIONS.
    LOGIC GATES :
    THE GATES WE USE IN THE FULL SUBTRACTOR ARE:
    NOT GATE
    AND GATE
    OR GATE
    XOR GATE
    THE GATES ARE ARRANGED WITHTO 2 HALF SUBTRACTORS TO MAKE A
    FULL SUBTRACTOR.

    OR GATE AND GATE NOT GATE XOR GATE


    FULL SUBTRACTOR:
    A full subtractor is a combinational circuit that performs subtraction of two
    bits, one is minuend and other is subtrahend, taking into account borrow of the
    previous adjacent lower minuend bit. This circuit has three inputs and two
    outputs. The three inputs A, B and Bin, denote the minuend, subtrahend, and
    previous borrow, respectively. The two outputs, D and Bout represent the
    difference and output borrow, respectively.
    TRUTH TABLE :
    INPUTS OUTPUT

    A B Bin DIFFERENCE BORROW

    0 0 0 0 0

    0 0 1 1 1

    0 1 0 1 1

    0 1 1 0 1

    1 0 0 1 0

    1 0 1 0 0

    1 1 0 0 0

    1 1 1 1 1
    K-MAPS :
    K-MAPS FOR THE ABOVE TRUTH TABLE
    BOOLEAN ALGEBRA:
    EXPRESSION FOR DIFFERENCE –
    D = A’B’Bin + A’BBin’ + AB’Bin’ + ABBin
    = Bin(A’B’ + AB) + Bin’(AB’ + A’B)
    = Bin( A XNOR B) + Bin’(A XOR B)
    = Bin (A XOR B)’ + Bin’(A XOR B)
    = Bin XOR (A XOR B) = (A XOR B) XOR Bin

    EXPRESSION FOR BORROW –


    B OUT = A’B’Bin + A’BBin’ + A’BBin + ABBin
    = A’B’Bin +A’BBin’ + A’BBin + A’BBin + A’BBin + ABBin
    = A’Bin(B + B’) + A’B(Bin + Bin’) + BBin(A + A’)
    = A’Bin + A’B + BBin
    CIRCUIT DIAGRAM :
    INPUT WAVE FORMS :
    OUTPUT WAVE FORM:
    DELAY ANALYSIS:
    THE FULL SUBTRACTOR IS MADE BY USING TWO HALF SUBTRACTOR’S.
    FULL SUBTRACTOR IS A COMBINATIONAL CIRCUIT.
    IT ALSO TAKES INTO CONSIDERATION BORROW OF THE LOWER
    SIGNIFICANT STAGE.
    THUS, FULL SUBTRACTOR HAS THE ABILITY TO PERFORM THE
    SUBTRACTION OF THREE BITS.
    THE BORROW GRAPH CANNOT BE PLOTED AS THE BORROW IS
    NEEDED FROM ANOTHER SOURCE.
    IT REQUIRES 2 XOR GATES, 2 AND GATES, 2 NOT GATES AND
    1 OR GATE TO COMPLETE THE CIRCUIT.
    CONCLUSION :
    These are generally employed for ALU (Arithmetic logic unit) in
    computers to subtract as CPU & GPU for the applications of graphics to
    decrease the circuit difficulty.
    Subtractors are mostly used for performing arithmetical functions like
    subtraction, in electronic calculators as well as digital devices.
    These are also applicable for different microcontrollers for arithmetic
    subtraction, timers, and program counter (PC)
    Subtractors are used in processors to compute tables, address, etc.
    It is also useful for DSP and networking based systems.
    REFERENCES:
    https://www.gatevidyalay.com/full-subtractor/
    https://www.geeksforgeeks.org/digital-logic-full-subtractor/
    https://www.researchgate.net/publication/305648408_Design_Analysis_of_Full_Subtra
    ctor_using_10T_at_45nm_Technology
    https://circuitdigest.com/tutorial/full-subtractor-circuit-and-its-construction
    https://www.electronics-tutorials.ws/combination/binary-subtractor.html
    http://www.eeeguide.com/full-subtractor/
    https://www.electronics-tutorial.net/combinational-logic-circuits/full-subtractor/
    THANK YOU

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