Seminar On FINFET Technology

Guided by: Prof.J.D.PRADHAN Submitted By: K.
Anurag
Regn no:0701227594
 INTRODUCTION
 PARTIALLY DEPLETED SOI
 PARASITIC BIPOLAR EFFECT
 SCALING FROM PD SOI TO FD SOI
 MAJOR DESIGN ISSUES
 FEATURES OF FINFET
 PROCESS FLOW OF FINFET
 APPLICATIONS OF FINFET
 SIMULATION RESULTS
 CONCLUSION
 REFERENCES
 Since the fabrication of MOSFET, the minimum channel
length has been shrinking continuously.
 The motivation behind this decrease is seen in high

speed devices and in very large scale integrated circuits.
 The limits most often cited are:-
 control of the density.
 finite subthreshold slope .
 quantum-mechanical tunneling .
 The channel depletion width must scale with the
channel length to contain the off-state leakage I off
this leads:-
 high doping concentration.
 The gate oxide thickness tox must also scale with

the channel length to maintain :-
 gate control.
 proper threshold voltage VT .

 The thinning of the gate dielectric results in :-
 gate tunneling leakage.
 degrading the circuit performance.
 power and noise margin.
 Partially depleted(PD)SOI was the first SOI
technology introduced for high performance
microprocessor applications.
 The PD SOI device is largely identical to the bulk device,
except for the addition of a buried oxide (“BOX”) layer
 The device offers several advantages for performance/
power improvement:-
 reduced junction capacitance.
 Parasitic bipolar effect.
 Hysteretic VT variation.
 Dynamic loading effects.

 Gate Oxide Tunneling Leakage
 Self heating
 Soft Error Rate
 Strained-Si channel And High-k Gate

 Finfet consists of a vertical Si fin controlled by
self_aligned double gate.
 Main Features of Finfet are:-
 Ultra thin Si fin for suppression of short channel effects
 Raised source/drain to reduce parasitic resistance and

improve currrent drive
 Symmetric gates yield great performance,but can built

asymmetric gates that target VT .
 Finfets are designed to use multiple fins to achieve
larger channel widths.
 Source/Drain pads connect the fins in parallel.
 As the number of fins is increased ,the current

through the device increases.
 .For eg: A 5 fin device 5 times more current than

single fin device.
 A conventional SOI wafer can be used as starting
material for:-
 Sacrificial oxidations.
 Masked ion implantations.
 specialized passive elements.
 Gate deposition and etch.

 DG devices like Fin FETs offer unique opportunities for
microprocessor design.compared to a planar process in
the same technology node,
 FinFETs have reduced channel and gate leakage currents.

This can lead to considerable power reductions when
converting a planar design to fin FET technology.
 Utilizing fin FETs would lead to a reduction in total power

by a factor of two, without compromising performance.
 Another possibility to save power arises when both gates

can be controlled separately.
 The second gate can be used to control the threshold voltage of the
device, thereby allowing fast switching on one side and reduced
leakage currents when circuits are idle.
 Finally, separate access to both gates could also be used to design

simplified logic gates.
 This would also reduce power, and save chip area, leading to smaller,
more cost-efficient designs. However chip designs using finFETs must
cope with quantization of device width.
 since every single transistor consists of an integral number of

fins,each fin having the same height.
 This article will present the simulation methodology of a self-aligned
double-gate MOSFET structure (FinFET) using SILVACO 3-D simulation
suite.
 Device Features:-
 A transistor is formed in a vertical ultra –thin Si fin and is controlled by a

double-gate, which considerably reduced short channel effects.
 the two gates are self aligned and are aligned to S/D.
 S/D is raised to reduce the access resistance.
 Up to date gate process: low temperature, high -k dielectrics can be

used .
 The 3-D SILVACO simulation
suite including Device3D,
DevEdit3D and TonyPlot3D,
allows device engineers to
study deep sub-micron devices
which are 3-D by nature like
the FinFET presented above.
 A 3-D FinFET structure was

designed by using DevEdit3D.
This is an advanced tool for
structure editing and mesh
generation.
 Sub 50-nm FinFETs
were successfully
simulated using 3-D
SILVACO simulation
tools.
 Simulations show that this structure should be scalable
down to 10 nm.
 This structure was fabricated by forming the S\D before

the gate.
 Further performance improvement is possible by using a

thinner gate dielectric and thinner spacers.
 FinFET is similar to the conventional MOSFET with

regard to layout and fabrication.
 . It is an attractive successor to the single gate MOSFET by
virtue of its superior electrostatic properties and
comparative ease of manufacturability.
 Industrial research groups such as Intel, IBM and AMD

have shown interests in developing similar devices, as well
as mechanisms to migrate mask layouts from Bulk-MOS
to FinFETs.
 Design Issues such as high quality ultra thin fin

lithography and source\drain resistance need to be
resolved and a high-yield process flow needs to be
established by process researchers before FinFETs can be
used in commercial.
 S. Thompson, P. Packan and M. Bohr, “MOS scaling ,
Transistor challenges for the 21st century,” Intel
Tech.J.,vol.Q3 pp1-19,1998.
 C.H.Wann, H. Noda, T. Tanaka, M.Yoshida and C. Hu, “A

comparative study of advanced MOSFET concepts ,” IEEE
Trans. Electron Devices, vol. 43, no. 10, pp 1742-1753, Oct.
1996
 X. Huang, W.C. Lee, C.Kuo, D.Hisamoto, L. Chang, J.

Keidzerski, E. Anderson, H.Takeuchi, Y.K. Choi, K.Asano.

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Guided by: Prof.J.D.PRADHAN Submitted By: K.

 The motivation behind this decrease is seen in high

 The limits most often cited are:-

 control of the density.

 finite subthreshold slope .

 high doping concentration.

 The gate oxide thickness tox must also scale with

 proper threshold voltage VT .

 reduced junction capacitance.

 Parasitic bipolar effect.

 Dynamic loading effects.

 Soft Error Rate

 Strained-Si channel And High-k Gate

 Main Features of Finfet are:-

 Ultra thin Si fin for suppression of short channel effects

 Raised source/drain to reduce parasitic resistance and

 Symmetric gates yield great performance,but can built

 Source/Drain pads connect the fins in parallel.

 As the number of fins is increased ,the current

 .For eg: A 5 fin device 5 times more current than

 Masked ion implantations.

 specialized passive elements.

 Gate deposition and etch.

 FinFETs have reduced channel and gate leakage currents.

 Utilizing fin FETs would lead to a reduction in total power

 Another possibility to save power arises when both gates

 Finally, separate access to both gates could also be used to design

 since every single transistor consists of an integral number of

 A transistor is formed in a vertical ultra –thin Si fin and is controlled by a

 S/D is raised to reduce the access resistance.

 Up to date gate process: low temperature, high -k dielectrics can be

 A 3-D FinFET structure was

 This structure was fabricated by forming the S\D before

 Further performance improvement is possible by using a

 FinFET is similar to the conventional MOSFET with

 Industrial research groups such as Intel, IBM and AMD

 Design Issues such as high quality ultra thin fin

 C.H.Wann, H. Noda, T. Tanaka, M.Yoshida and C. Hu, “A

 X. Huang, W.C. Lee, C.Kuo, D.Hisamoto, L. Chang, J.

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