Falcon-E : Introduction

• Eight GPRs: R0, R1, …, R7; 32-bits each

• Two 32-bit special purpose registers:
 BP and SP
• Two 32-bit system registers transparent to
the programmer: PC and IR
• Memory word size: 32 bits
• Memory space size: 232 bytes
• Memory organization: 232 x 8 bits
• Memory accessed in 32 bit words
( i.e., 4 byte chunks)
• Little-endian byte storage 1
Review

2
 CS501
Advanced Computer
Architecture

Lecture10

Dr.Noor Muhammad Sheikh

3
Programmer’s view of the Falcon-E

31 0
R0 7 0 7 0
R1 0
: 1
R7 2
Register file :
BP :
:
SP

IR 232-1
PC

CPU Main memory Input/Output

4
 Falcon-E Notation

• [R3] means contents of register R3

• M[8] means contents of memory
location 8
• A memory word at address 8 is
defined as the 32 bits at addresses
11, 10, 9, and 8 (little-endian)
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 Falcon-E Notation
• Special notation for 32-bit memory words
M[8]<31…0>:=M[11]©M[10]©M[9]©M[8]
(© is used to represent concatenation)
 Memory addresses

7 0
8 M[8] One memory “word”
9 M[9]
31 24 23 16 15 8 7 0
10 M[10]
M[11] M[10] M[9] M[8]
11 M[11]
MS Byte LS Byte

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Falcon-E : instruction formats
31 27 26 0

Type A O pcode D is p la c e m e n t / N o t U s e d

31 27 26 24 23 0

Type B O pcode ra D is p la c e m e n t / Im m e d ia te

31 27 26 24 23 21 20 0

Type C O pcode ra rb D is p la c e m e n t / Im m e d ia te

31 27 26 24 23 21 20 18 17 4 3 0

Type D O pcode ra rb rc U n u sed fu n c

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 Encoding for the GPRs
to be used in place of ra, rb, or rc
Register Code Register Code

R0 000 R4 100

R1 001 R5 101

R2 010 R6 110

R3 011 R7 111

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 Encoding for the SPRs
to be used in place of rb in lds and sts instructions

Register Code

SP 000

BP 001

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 31 27 26 0

Type A O pcode D is p la c e m e n t / N o t U s e d

 nop (op-code = 0)
useful in pipelining
 ret (op-code = 15)
 iret (op-code = 17)
 near jmp (op-code = 18)

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Type B
31 27 26 24 23 0

O pcode ra D is p la c e m e n t / Im m e d ia te

 push (op-code = 8) pushes register to stack

push R4
 pop (op-code = 9) pops data from stack to register

pop R7
 ld (op-code = 10)
ld R7, [1254h]
 st (op-code = 12)
st R7, [1254h]

11
Type C
31 27 26 24 23 21 20 0

O pcode ra rb D is p la c e m e n t / Im m e d ia te

 lds (op-code = 4) load special purpose register

lds SP, R1 R[1] SP
 sts (op-code = 5) store special purpose register
sts R3, BP BP R[3]
 in (op-code = 6) load register from IO device
in R5, R4(100) R[5] IO[R[4]+100]
 out (op-code = 7) store register to IO device
out R8, R6(36) IO[R[6]+36] R[8]
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Type C 31

O pcode
27 26

ra
24 23

rb
21 20

Im m e d ia te
4 3

fu n c
0

If the constant
 addi (op-code = 2) immediate 2’s complement additionis negative,
this becomes
addi R3, R4, 56 R[3] R[4] + 56 a subtract
instruction

 andi (op-code = 2) immediate logical AND

andi R3, R4, 56 R[3] R[4] & 56

 ori (op-code = 2) immediate logical OR

ori R3, R4, 56 R[3] R[4] ~ 56

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Type D
31 27 26 24 23 21 20 18 17 4 3 0

O pcode ra rb rc U nused fu n c

 add (op-code = 1) 2’s C register addition register addressing mode

add R3, R5, R6 R[3] R[5] + R[6]

 sub (op-code = 1) 2’s C register subtraction
sub R3, R5, R6 R[3] R[5] - R[6]
 and (op-code = 1) logical AND operation between registers

and R8, R3, R4 R[8] R[3] & R[4]

 or (op-code = 1) logical OR operation between registers

or R8, R3, R4 R[8] R[3] ~ R[4]

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FUNCTIONAL GROUPS OF
INSTRUCTIONS

Opcode Function
Control Instructions Mnemonic
Dec Bin Dec Bin

No Operation nop 0 00000 -

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 FUNCTIONAL GROUPS OF
INSTRUCTIONS
Opcode Function
Arithmetic Instructions Mnemonic
Dec Bin Dec Bin

Add add 1 00001 0 0000

Add Immediate addi 2 00010 0 0000

Subtract sub 1 00001 1 0001

Subtract Immediate subi 2 00010 1 0001

Multiply mul 1 00001 2 0010

Multiply Immediate muli 2 00010 2 0010

Divide div 1 00001 3 0011

Divide Immediate divi 2 00010 3 0011

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 FUNCTIONAL GROUPS OF
INSTRUCTIONS
Opcode Function
Logic Instructions Mnemonic
Dec Bin Dec Bin

And and 1 00001 4 0100

And Immediate andi 2 00010 4 0100

Or or 1 00001 5 0101

Or Immediate ori 2 00010 5 0101

Xor xor 1 00001 6 0110

Xor Immediate xori 2 00010 6 0110

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 FUNCTIONAL GROUPS OF
INSTRUCTIONS
Opcode Function
Shift and Rotate
Mnemonic
Instructions Dec Bin Dec Bin

Shift Left shl 1 00001 8 1000

Shift Left Immediate Count shli 2 00010 8 1000

Rotate Left rol 1 00001 9 1001

Rotate Left Immediate Count roli 2 00010 9 1001

Shift Right shr 1 00001 10 1010

Shift Right Immediate Count shri 2 00010 10 1010

Shift Right Arithmetic sra 1 00001 11 1011

Shift Right Arithmetic

Immediate Count
srai 2 00010 11 1011
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 FUNCTIONAL GROUPS OF
INSTRUCTIONS
Opcode Function
Mnemonic
Data Transfer Instructions Dec Bin Dec Bin

Move Immediate to GPR movi 3 00011 -

Load Special Purpose Register from GPR lds 4 00100 -
Store Special Purpose Register to GPR sts 5 00101 -
Load Register from IO in 6 00110 -
Store Register to IO out 7 00111 -
Push GPR to Stack push 8 01000 -
Pop GPR from Stack pop 9 01001 -
Load GPR from Memory (Direct
Addressing)
ld 10 01010 -

Load GPR from Memory (Displacement

Addressing)
ld 11 01011 -

Store GPR to Memory (Direct

Addressing)
st 12 01100 -

Store GPR to Memory (Displacement 19

Addressing)
st 13 01101 -
 FUNCTIONAL GROUPS OF
INSTRUCTIONS
Opcode Function
Procedure Calls/Interrupts Mnemonic
Dec Bin Dec Bin

Call call 14 01110 -

Return ret 15 01111 -

Interrupt int 16 10000 -

Interrupt Return iret 17 10001 -

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 FUNCTIONAL GROUPS OF
INSTRUCTIONS
Opcode Function
Branch Instructions Mnemonic
Dec Bin Dec Bin

Near Jump (Relative) jmp 18 10010 -

Far Jump (Direct) jmp 19 10011 -
Branch If Equal (Relative) bre 20 10100 0 0000
Branch If Equal (Direct) bre 21 10101 0 0000
Branch If Not Equal (Relative) bne 20 10100 1 0001

Branch If Not Equal (Direct) bne 21 10101 1 0001

Branch If Less (Relative) bl 20 10100 2 0010

Branch If Less (Direct) bl 21 10101 2 0010
Branch If Greater (Relative) bg 20 10100 3 0011

Branch If Greater (Direct) bg 21 10101 3 0011

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23
24
25
26
27
28
29
30
31
32
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34
35
 Instruction Length
• Fixed versus variable
• 16 bit versus 32 bit

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 Instruction Types and Sub-types

EAGLE FALCON-A FALCON-E SRC

Types 4 4 4 4

Sub-types - 2 4 3

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Maximum Number of Operands
EAGLE FALCON-A FALCON-E SRC

2 3 3 3

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 Number and Size of GPR

EAGLE FALCON-A FALCON-E SRC

8 registers, 8 registers, 8 registers, 32 registers

16 bit wide 16 bit wide 32 bit wide 32 bit wide

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 Memory Specs.
Memory EAGLE FALCON-A FALCON-E SRC
Specs.

Memory
216 216 232 232
Space

Memory
216 x 8 216 x 8 232 x 8 232 x 8
Organization

Memory
Word Size
16 bit 16 bit 32 bit 32 bit
Memory
16 bits 16 bits 32 bits 32 bits
Access

Memory Little Endian Big Endian Little Endian Big Endian

Storage 40
 Data Transfer Instructions

Data Transfer Advantages Disadvantages

Register to Simple, faster, constant CPI, Higher instruction
Register Easier to pipeline. count, longer program
codes

Register to Separate load instruction Variable CPI due to

Memory eliminated, good code different operand
density locations

Memory to Most compact, small Variable CPI, variable

Memory number of registers required instruction size,
memory bottleneck.
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 Data Transfer Instructions

Instructions EAGLE FALCON-A FALCON-E SRC

Register to a2r, r2a mov lds, sts lar

Register (only from
PC)

Register to ldacc, stacc load, store ld, st ld, st

Memory

Memory to - - - -
Memory

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Control Flow Instructions

• Branches (conditional)
• Jumps (unconditional)
• Calls (procedure calls)
• Returns (procedure returns)

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 Branch Options
• Condition Codes
– test special bits set by ALU
– specific ordering of instructions required
– EAGLE uses condition codes for branch condition evaluation
• Condition Register
– tests arbitrary registers
– special register required.
– none of our processors allocate a specific register for storing branch
results.
• Compare and Branch
– comparison is part of branch
– complex
– all the processors, SRC, FALCON-E, FALCON-A & EAGLE have
compare and branch instructions.

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 Size of Jumps

Processor Displacement size

EAGLE 8 bits for both conditional and unconditional.

FALCON-A 8 bits for both conditional and unconditional.

FALCON-E 27 bits (unconditional jump),

21 or 32 bits (conditional jumps)
SRC 32 bits for both conditional and unconditional jumps.

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 Addressing Modes
 Specify a constant, a register or a location
in memory.
 Common addressing modes are
– Immediate 123
– Register R3
– Direct [123]
– Register Indirect M[R3]
– Displacement M[R3+123]
– Relative [PC+123]
– Indexed or scaled
– Auto increment/ decrement
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 Addressing Modes
EAGLE FALCON-A FALCON-E SRC
Immediate Immediate Immediate Immediate

- - Direct Direct

Register Register Register Register

Register Indirect Register Indirect Register Indirect Register Indirect

- - - Relative

Displacement Displacement Displacement Displacement

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 Size of Displacement Field
Processor Number of bits in displacement field

SRC 17 or 22 bits depending on the

instruction type
FALCON-E 21 or 24 bits depending on the
instruction type
FALCON-A 5 bits for load and store instruction

EAGLE 8 bits for ldacc and stacc

instructions
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 Size of Immediate Field
Processor Number of bits in the immediate field

EAGLE 8 bits

FALCON-A 5 or 8 bits

FALCON-E 17 or 24 bits depending on the

instruction
SRC 17 or 22 bits

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 Similar Instructions
(Arithmetic)
Instruction EAGLE FALCON-A FALCON-E SRC
Add add add add add

Add addi addi addi addi

Immediate
Subtract sub sub sub sub

Subtract subi subi subi -

Immediate
Multiply mul mul mul -

Divide div div div -

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 Similar Instructions
(Logic)
Instruction EAGLE FALCON-A FALCON-E SRC
And and and and and

And andi andi andi andi

Immediate
Or or or or or

Or ori ori ori ori

Immediate
Not not not not not

Neg neg neg - -

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 Similar Instructions
(Shift)
Instruction EAGLE FALCON-A FALCON-E SRC

Shift right shiftr shiftr shr shr

Shift right - - srai shr
immediate
Circular - - rol shc
shift
Shift left shiftl shiftl shl shl

Shift right asr asr sra shra

arithmetic 52
 Similar Instructions
(Control)

Instruction EAGLE FALCON-A FALCON-E SRC

No nop nop nop nop

operation
Halt halt halt - stop
Reset reset reset - -

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 Similar Instructions
(Branch)
Instruction EAGLE FALCON-A FALCON-E SRC
Unconditional br jump jmp br
branch
Branch if zero brz jz - brzr

Branch if non brnz jnz - brnz

zero
Branch if brp jpl - brpl
positive
Branch if brn jmi - brmi
negative

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 Similar Instructions
(Calls and Interrupts)

Instruction EAGLE FALCON-A FALCON-E SRC

Procedure - call call brl
call
Interrupt - int int -
Interrupt - iret iret -
return

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 Similar Instructions
(Data Movement)
Instruction EAGLE FALCON-A FALCON-E SRC
Load ldacc load ld ld

Store stacc store st st

Move mov mov - -

Move movi movi movi la

immediate
In in in in -

Out out out out -

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 Instructions Unique to EAGLE

EAGLE has a minimal ISA with following

unique instructions
• movia
• a2r
• r2a
• cla

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Instructions Unique to FALCON-A

ret
PC R[ra];

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 Instructions Unique to FALCON-E
• push
• pop
• ldr
• str
• bl
• bg
• muli
• divi
• xor, xori
• ror,rori
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 Instructions Unique to SRC

• ldr
• lar
• str
• brlnv
• brlpl
• brlmi
• brlzr
• brlnz
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 Problem Comparison
Given is the code for a simple C statement, a=(b-2)+4c and its implementation
in all the four processors.

EAGLE FALCON-A FALCON-E SRC

.org 100 .org 100 .org 100 .org 100
a: .dw 1 a: .dw 1 a: .dw 1 a: .dw 1

.org 200 .org 200 .org 200

.org 200
ldacc b load r1, b ld r1, b ld r1, b
a2r r1 subi r2, r1, 2 subi r2, r1,2 addi r2,r1,-2
subi r1,2 load r3, c ld r3, c ld r3, c
a2r r1 shiftl r3,r3,2 muli r3,r3, 4 shl r3, r3, 2
ldacc c add r4,r2,r3 add r4, r3,r2 add r4,r2,r3
a2r r2 store r4, a store r4,a st r4, a
shl r2, 2
r2a r2
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add r1