William Stallings

Computer Organization
and Architecture
8th Edition

Lecture 3
Top Level View of Computer
Function and Interconnection
Program Concept
• Hardwired systems are inflexible
• General purpose hardware can do
different tasks, given correct control
signals
• Instead of re-wiring, supply a new set of
control signals
What is a program?
• A sequence of steps
• For each step, an arithmetic or logical
operation is done
• For each operation, a different set of
control signals is needed
Function of Control Unit
• For each operation a unique code is
provided
—e.g. ADD, MOVE
• A hardware segment accepts the code and
issues the control signals

• We have a computer!
Components
• The Control Unit and the Arithmetic and
Logic Unit constitute the Central
Processing Unit
• Data and instructions need to get into the
system and results out
—Input/output
• Temporary storage of code and results is
needed
—Main memory
Computer Components:
Top Level View
Instruction Cycle
• Two steps:
—Fetch
—Execute
Fetch Cycle
• Program Counter (PC) holds address of
next instruction to fetch
• Processor fetches instruction from
memory location pointed to by PC
• Increment PC
—Unless told otherwise
• Instruction loaded into Instruction
Register (IR)
• Processor interprets instruction and
performs required actions
Execute Cycle
• Processor-memory
—data transfer between CPU and main memory
• Processor I/O
—Data transfer between CPU and I/O module
• Data processing
—Some arithmetic or logical operation on data
• Control
—Alteration of sequence of operations
—e.g. jump
• Combination of above
Example of Program Execution
Instruction Cycle State Diagram
Interrupts
• Mechanism by which other modules (e.g.
I/O) may interrupt normal sequence of
processing
• Program
—e.g. overflow, division by zero
• Timer
—Generated by internal processor timer
—Used in pre-emptive multi-tasking
• I/O
—from I/O controller
• Hardware failure
—e.g. memory parity error
Program Flow Control
Interrupt Cycle
• Added to instruction cycle
• Processor checks for interrupt
—Indicated by an interrupt signal
• If no interrupt, fetch next instruction
• If interrupt pending:
—Suspend execution of current program
—Save context
—Set PC to start address of interrupt handler
routine
—Process interrupt
—Restore context and continue interrupted
program
Transfer of Control via Interrupts
Instruction Cycle with Interrupts
Program Timing
Short I/O Wait
Program Timing
Long I/O Wait
Instruction Cycle (with Interrupts) -
State Diagram
Multiple Interrupts
• Disable interrupts
—Processor will ignore further interrupts whilst
processing one interrupt
—Interrupts remain pending and are checked
after first interrupt has been processed
—Interrupts handled in sequence as they occur
• Define priorities
—Low priority interrupts can be interrupted by
higher priority interrupts
—When higher priority interrupt has been
processed, processor returns to previous
interrupt
Multiple Interrupts - Sequential
Multiple Interrupts – Nested
Time Sequence of Multiple Interrupts
INTERCONNECTION STRUCTURES
• A computer consists of a set of
components or modules of three basic
types (processor, memory, I/O) that
communicate with each other.
• Thus, there must be paths for connecting
the modules
• The collection of paths connecting the
various modules is called the
interconnection structure.
Connecting
• All the units must be connected
• Different type of connection for different
type of unit
—Memory
—Input/Output
—CPU
Computer Modules
I/O module
• From an internal (to the computer
system) point of view, I/O is functionally
similar to memory. There are two
operations, read and write.

• Further, an I/O module may control more

than one external device.

• We can refer to each of the interfaces to

an external device as a port and give each
a unique address (e.g., 0, 1, . . . ,M– 1).
Memory Connection
• Receives and sends data
• Receives addresses (of locations)
• Receives control signals
—Read
—Write
—Timing
Input/Output Connection(1)
• Similar to memory from computer’s
viewpoint
• Output
—Receive data from computer
—Send data to peripheral
• Input
—Receive data from peripheral
—Send data to computer
Input/Output Connection(2)
• Receive control signals from computer
• Send control signals to peripherals
—e.g. spin disk
• Receive addresses from computer
—e.g. port number to identify peripheral
• Send interrupt signals (control)
CPU Connection
• Reads instruction and data
• Writes out data (after processing)
• Sends control signals to other units
• Receives (& acts on) interrupts
Buses
• There are a number of possible
interconnection systems
• Single and multiple BUS structures are
most common
• e.g. Control/Address/Data bus (PC)
• e.g. Unibus (DEC-PDP)
What is a Bus?
• A communication pathway connecting two
or more devices
• Usually broadcast
• Often grouped
—A number of channels in one bus
—e.g. 32 bit data bus is 32 separate single bit
channels
• Power lines may not be shown
Bus Structure (system bus)
• A bus that connects major computer
components (processor, memory, I/O) is
called a system bus.
• A system bus consists, typically, of from
about 50 to hundreds of separate lines.
Each line is assigned a particular meaning
or function.
Data Bus
• Carries data
—Remember that there is no difference between
“data” and “instruction” at this level
• Width is a key determinant of
performance
—8, 16, 32, 64 bit
Address bus
• Identify the source or destination of data
• e.g. CPU needs to read an instruction
(data) from a given location in memory
• Address bus width determines maximum
memory capacity of system
—e.g. 8080 has 16 bit address bus giving 64k
address space
• Furthermore, the address lines are
generally also used to address I/O ports.
Control Bus
• Control and timing information
—Memory read/write signal
—Interrupt request
—Clock signals
Bus Interconnection Scheme
Big and Yellow?
• What do buses look like?
—Parallel lines on circuit boards
—Ribbon cables
—Strip connectors on mother boards
– e.g. PCI
—Sets of wires
Physical Realization of Bus Architecture
Single Bus Problems
• Lots of devices on one bus leads to:
—Propagation delays
– Long data paths mean that co-ordination of bus use
can adversely affect performance
– If aggregate data transfer approaches bus capacity
• Most systems use multiple buses to
overcome these problems
Traditional (ISA)
(with cache)
• There is a local bus that connects the
processor to a cache memory and that
may support one or more local devices.
• The cache memory controller connects the
cache not only to this local bus, but to a
system bus to which are attached all of
the main memory modules.
• The use of a cache structure insulates the
processor from a requirement to access
main memory frequently.
High Performance Bus
• It is possible to connect I/O controllers directly
onto the system bus.

• A more efficient solution is to make use of one or

more expansion buses for this purpose.

• An expansion bus interface buffers data transfers

between the system bus and the I/O controllers
on the expansion bus.

• This arrangement allows the system to support a

wide variety of I/O devices and at the same time
insulate memory-to-processor traffic from I/O
traffic.
Elements of Bus Design
• Although a variety of different bus implementations exist, there
are a few basic parameters or design elements that serve to
classify and differentiate buses. Table 3.2 lists key elements.
Bus Types
• Dedicated
— Separate data & address lines
— Physical dedication refers to the use of multiple buses,
each of which connects only a subset of modules.
— The potential advantage of physical dedication is high
throughput, because there is less bus contention.
A disadvantage is the increased size and cost of the
system.
• Multiplexed
— Shared lines
— Address valid or data valid control line
— Advantage - fewer lines
— Disadvantages
– More complex control
– Ultimate performance
Bus Arbitration
• More than one module may need control
of the bus.
—e.g. CPU and DMA controller
• Only one module may control bus at one
time
• Some method of arbitration is needed
• Arbitration may be centralised or
distributed
Centralised or Distributed Arbitration
• Centralised
—Single hardware device controlling bus access
– Bus Controller or
– Arbiter is responsible for allocating time on the bus
—May be part of CPU or separate
• Distributed
—Each module may claim the bus
—Control logic and on all modules
—i.e. each module contains access control logic
and the modules act together to share the bus
 With both methods of arbitration, the purpose is to
designate one device, either the processor or an I/O
module, as master.
Timing
• Refers to the way in which events are co-
ordinated on the bus.
• Synchronous
—The occurrence of Events on the bus is
determined by clock signals
—The bus includes a clock line upon which a
clock transmits a regular sequence of
alternating 1s and 0s of equal duration
– Control Bus includes clock line
– A single 1-0 transmission is a bus cycle or clock
cycle
– All other devices on a bus can read clock line
– Usually sync on leading edge
– Usually a single cycle for an event
Synchronous Timing Diagram
Asynchronous timing
• With asynchronous timing, the occurrence of
one event on a bus follows and depends on
the occurrence of a previous event.
• In the simple read example of Figure 3.20a, the
processor places address and status signals on
the bus.
• After pausing for these signals to stabilize, it
issues a read command, indicating the presence
of valid address and control signals
Asynchronous Timing – Read Diagram
Asynchronous Timing – Write Diagram
BUS WIDTH

• The width of the data bus has an impact

on system performance:
—The wider the data bus, the greater the
number of bits transferred at one time.

• The width of the address bus has an

impact on system capacity:
—the wider the address bus, the greater the
range of locations that can be referenced.
DATA TRANSFER TYPE
• All buses support both write (master to
slave) and read (slave to master)
transfers.
• In the case of a multiplexed address/data bus,
the bus is first used for specifying the address
and then for transferring the data.
• For a read operation, there is typically a wait
while the data are being fetched from the slave
to be put on the bus.
PCI Bus
• Peripheral Component Interconnection
• Intel released to public domain
• 32 or 64 bit
• 50 lines
PCI Bus Lines (required)
• Systems lines
—Including clock and reset
• Address & Data
—32 time mux lines for address/data
—Interrupt & validate lines
• Interface Control
• Arbitration
—Not shared
—Direct connection to PCI bus arbiter
• Error lines
PCI Bus Lines (Optional)
• Interrupt lines
—Not shared
• Cache support
• 64-bit Bus Extension
—Additional 32 lines
—Time multiplexed
—2 lines to enable devices to agree to use 64-
bit transfer
• JTAG/Boundary Scan
—For testing procedures
PCI Commands
• Transaction between initiator (master)
and target
• Master claims bus
• Determine type of transaction
—e.g. I/O read/write
• Address phase
• One or more data phases
PCI Read Timing Diagram
PCI Bus Arbiter
PCI Bus Arbitration
Foreground Reading
• Stallings, chapter 3 (all of it)
• www.pcguide.com/ref/mbsys/buses/

• In fact, read the whole site!

• www.pcguide.com/