System Design

Through Verilog
(R16 - IV B.Tech.,I Sem, ECE)

Presented
by
RAKESH DASARI
 UNIT – I
INTRODUCTION TO VERILOG:
Verilog as HDL
Levels of design Description
Concurrency
Simulation and Synthesis LANGUAGE CONSTRUCTS AND
Functional Verification CONVENTIONS:
System Tasks • Introduction, Keywords, Identifiers,
Programming Language Interface White Space Characters, Comments,
(PLI) • Numbers
Module • Strings
Simulation and Synthesis Tools • Logic Values
Test Benches. • Strengths
• Data Types
• Scalars and Vectors
• Parameters
• Operators.
INTRODUCTION TO VERILOG:
Verilog as HDL
Levels of design Description
Concurrency
Simulation and Synthesis
Functional Verification
System Tasks
Programming Language Interface (PLI)
Module
Simulation and Synthesis Tools
Test Benches.
Verilog as HDL
Verilog aimed at providing a functionally tested and a verified

design description for the target FPGA or ASIC.

The language has a dual function :

 fulfilling the need for a design description.

 fulfilling the need for verifying the design for functionality

and timing constraints like propagation delay, critical path

delay, slack, setup, and hold times.
Levels of design Description

Circuit or Switch Level

Gate Level

Data Level

Behavioral Level
Circuit or Switch Level
At the circuit level, a switch is

the basic element with which

digital circuits are built.
Switches can be combined to form

inverters and other gates at the

A simple
next higher level of abstraction.
Inverter circuit
at the Switch Level
Gate Level
At the next higher level of

abstraction, design is carried

out in terms of basic gates.
All the basic gates are
A Simple AND gate
available as ready modules represented
at the Gate Level
called “Primitives”.
Data Flow
Data flow is the next higher level of abstraction.

All possible operations on signals and variables are

represented here in terms of assignments.

An A-O-I gate represented as a

data flow type of relationship.
Behavioral Level
Behavioral level constitutes the highest level of design

description; it is essentially at the system level itself.

With the assignment possibilities, looping constructs and

conditional branching possible, the design description

essentially looks like a “C” program.

An A-O-I gate in
psecdo code at
Behavioral Level
The overall design structure in verilog
The possibilities of design description statements and assignments at

different levels necessitate their accommodation in a mixed mode.

In fact the design statements coexisting in a design module is a

significant characteristic of Verilog.

 Thus Verilog facilitates the mixing of the the four 4 levels of design.

 A design built at data flow level can be instantiated to form a

structural mode design. Data flow assignments can be incorporated in

designs which are basically at behavioral level.
Verilog Language Concepts
Concurrency

Simulation and Synthesis

Functional Verification

System Tasks

Programming Language Interface (PLI)

Concurrency
In an electronic circuit all the units are to be active and

functioning concurrently. The voltages and currents in the

different elements in the circuit can change simultaneously.
In turn the logic levels too can change.
Simulation of such a circuit in an HDL calls for concurrency

of operation.
All the activities scheduled at one time step are completed

and then the simulator.

Contd….
Verilog simulators are built to simulate concurrency.

 Concurrency is achieved by proceeding with simulation in equal time steps.

The time step is kept small enough to be negligible compared with the

propagation delay values.

 All the activities scheduled at one time step are completed and then the

simulator advances to the next time step and so on.

In some cases the circuit itself may demand sequential operation as with data

transfer and memory-based operations.

 Only in such cases sequential operation is ensured by the appropriate usage of

sequential constructs from Verilog HDL.

Simulation and Synthesis
The design that is specified and entered as described earlier is

simulated for functionality and fully debugged.

Translation of the debugged design into the corresponding hardware

circuit (using an FPGA or an ASIC) is called “synthesis.”

The circuits realized from them are essentially direct translations of

functions into circuit elements.

The process is carried out successively with each of the behavioral

level modules until practically the full design is available as a pack

of modules at gate and data flow levels.
Functional Verification
Testing is an essential ingredient of the VLSI design

process as with any hardware circuit.

It has two dimensions to it – functional tests and timing

tests.
Testing or functional verification is carried out by setting

up a “test bench” for the design.

Test Inputs for Test Benches
Test inputs can be purely combinational, periodic, numeric

sequences, random inputs, conditional inputs, or combinations of

these.
As the circuit design proceeds, one develops smaller blocks and

groups them together to form bigger circuit units. The process is

repeated until the whole system is fully built up. Every stage calls
for tests to see whether the subsystem at that layer behaves in the
manner expected.
Contd…
Such testing calls for two types of observations:

 Study of signals within a small unit when test inputs are

given to the whole unit.

 Isolation of a small element and doing local test to facilitate

debugging.
Constructs for modeling timing delays
Any basic gate has propagation delays and transmission delays

associated with it.

often one reaches a stage where the expected function is not

realized due to large time delay.

Verilog has constructs for modeling the following delays:

 Gate Delay

 Net Delay

 Path Delay

 Pin-to-Pin delay
Contd…
In addition, a design can be tested for setup time, hold time, clock-

width time specifications, etc.

 Such constructs or delay models are akin to the finite delay time, rise

time, fall time, path or propagation delays, etc., associated with real
digital circuits or systems.
The use of such constructs in the design helps simulate realistic

conditions in a digital circuit.

With such testing, one can estimate the minimum frequency of

operation, the maximum speed of response, or typical response times.

System Tasks
A number of system tasks are available in Verilog.

Though used in a design description, they are not part of

it.
Some tasks facilitate control and flow of the testing

process.
Contd…
A set of system functions add to the flexibility of test

benches: They are of three categories:

 Functions that keep track of the progress of simulation time

 Functions to convert data or values of variables from one

format to another
 Functions to generate random numbers with specific
distributions.
There are other numerous system tasks and functions
Programming Language Interface (PLI)
Programming Language Interface (PLI) is a way to

provide Application Program Interface (API) to Verilog

HDL.
Essentially it is a mechanism to invoke a C function from

a Verilog code.
PLI is primarily used for doing the things which would

not have been possible otherwise using Verilog syntax.

Contd…
One can read data from a file and pass it to a Verilog module

as input. Such data can be test vectors or other input data to

the module. Similarly, variables in Verilog modules can be
accessed and their values written to output devices.
Delay values, logic values, etc., within a module can be

accessed and altered.

Blocks written in C language can be linked to Verilog

modules.
Module
Any Verilog program begins with a keyword – called a

“module.”
A module is the name given to any system considering it

as a black box with input and output terminals as shown in

Figure
The terminals of the module are referred to as ‘ports’.
Contd…

Representation of a MODULE
as block box with its ports
Contd…
The ports attached to a module can be of three types:

 input ports through which one gets entry into the module

 output ports through which one exits the module.

 inout ports: These represent ports through which one gets

entry into the module or exits the module

• All the constructs in Verilog are centered on the module.

Module Syntax
module module_name (port_list);
Input, output, inout declaration
Intermediate variable declarations

Functional Description

(gate / switch / data flow / Behv.)

end module
Contd…
• A module comprises a number of “lexical tokens” arranged
according to some predefined order.
• The possible tokens are of seven categories.

 Keywords
 Identifiers
 White spaces
 Comments
 Numbers
 Strings
 Operators
Contd…

Structure of a typical Simulation module

Contd…
Example of a module

Eight I/P NAND Gate IC 7430

Contd…

8-I/P Gate IC 7430 Structure of the Gat module

Contd…
 The same type of IC – 7430 – may be repeatedly used in a circuit. Each time it

is used, a different name is assigned to it in the design sheet. Part of such a

typical design sheet will look as in Figure 2.8.

Part of the
circuit
diagram of a
typical digital
circuit
Contd…
 The below table allows us to identify each type of IC to be used and put in its

proper place.

Partial list of IC numbers and their types for a typical design

 An automated design description can use a module defined above, repeatedly

in a number of places as in the circuit of above Figure . Each such use is an

“instantiation.”
 A typical instantiation of the module defined above has the form shown in

below Figure . The following observations are in order here:

Contd…
The designer has defined a specific function within a module;

the module is assigned the name “nand_gate.”

The nand_gate can be invoked (instantiated) by him in a design

as many times as desired.

Each instantiation has to be assigned a separate identifier name

by him (called “IC1”, “IC2”, etc.).

As part of the instantiation declaration, the input and output

terminals are to be defined. The convention followed is to stick

to the same order as in the module declaration. It is further
illustrated in Figure 2.9.
Contd…

Instantiations of module nand_gate

in another module
Contd…
Some modules may have a large number of ports. Sticking to

the order of the ports in an instantiation is likely to cause

(human) errors. An alternative form of instantiation is also
possible – shown in below Figure
.
Contd…

A Typical circuit block and its instantiation

Contd…
The following aspects of the modules and their instantiation

are noteworthy:
 Each module can be defined only once.

 Module definitions are to be done independently. One

module cannot be defined inside another – they cannot be

nested.
 Any module can be instantiated inside another any number

of times. Each instantiation has to be done with a separate

name assigned to it.
Simulation and Synthesis Tools
A variety of Software tools related to VLSI design is available.

Two of them are

- Modelsim and
- Leonardo Spectrum of Mentor Graphics.
Modelsim has been used to simulate the designs.

Leonardo Spectrum has been used to obtain the synthesized

circuits
Contd…
Use of Modelsim SE 5.5

 Editing and Compilation

 Simulation

 Observing Waveforms

Synthesis Conversion of the code into hardware logic and

fitting it into an FPGA or ASIC to realize the circuit is

termed “Synthesis.” We have used the Mentor Graphics
Synthesis tool called “Leonardo Spectrum” for the purpose.
Contd…
Synthesis

The window in Leonardo spectrum to do settings for synthesis

Test Bench
Any digital circuit that has been designed and wired goes

through a testing process before being declared as ready for use.

 Testing involves studying circuit behavior under simulated

conditions for the following:

Check and ensure that all functions are carried out as desired. It

is the test for the static behavior of the circuit. A set of logic
input values are applied at selected points and the logic values
at another set of points observed.
Contd…
Check and ensure that all the functional sequences are carried out as

desired. It is one of the tests for the dynamic behavior of the circuit.
It may call for the generation of specific input sequences with
respect to time, applying them to the circuit and observing selected
outputs.
Check for the timing behavior: One tests for the propagation and

other types of delays here. A variety of tests may have to be carried

out. It may involve observation of variations in the signals at
selected points, measuring the time delay between specified events,
measuring pulse widths, and so on.
Contd…
Simulated testing is a time-based activity. It is usually

carried out in simulated time.

With any simulation tool the simulation progresses

through equal simulation time steps. The time step can be

1 fs, 1 ps, 1 ns and so on.
Test Bench Syntax
A test bench is HDL code that allows you to provide a

documented, repeatable set of stimuli.

module tb_module_name ;
Input, output, inout declaration
Intermediate variable declarations
Stimulus (initial / always)
End module
Example of 2-i/p and gate
module test_and;
reg a1, a2;
wire b;
#3 a2 = 0;
Initial
#1 a2 = 1;
Begin
end
a1 = 0;
a2 = 0; and g1(b, a1, a2);
#3 a1 = 1; initial $monitor
#1 a1 = 0; ( $time, “a1 = %b, a2 = %b,
#2 a2 = 1; b = %b”’ a1, a2, b);
#4 a1 = 1; initial #100 $finish;
#3 a2 = 0; endmodule
#1 a2 = 1;
Contd…
The keyword initial is followed by a sequence of statements

between the keywords begin and end.

The “# 3” implies a time delay or wait time of 3 time steps in

simulation.
At 0 simulation time the logic variables a1 and a2 are

assigned the logic level 0.

With a delay of 3 ns a1 is reassigned the logic value of 1.
Contd…
With a further delay of 1 ns – that is, at the 4th ns - a1 is

reverted to the logic level 0.

Similarly at the 6th, 10th, 13th and 14th ns values of

simulation time, further changes are made to a1 and a2.

Note that every time value specified here is an increment

in simulation time.
The output obtained by running the module
0 a1 = 0 a2 = 0 b=0
3 a1 = 1 a2 = 0 b=0
4 a1 = 0 a2 = 0 b=0
6 a1 = 0 a2 = 1 b=0
10 a1 = 1 a2 = 1 b=1
13 a1 = 1 a2 = 0 b=0
14 a1 = 1 a2 = 1 b=1
Contd…
Summarizing testing constitutes three activities:

 Generation of the test signals – under the “initial”

banner.
 Application of the test signal to the circuit under test –

through instantiation.
 Observing selected signal values – through the
$monitor statement
LANGUAGE CONSTRUCTS AND
CONVENTIONS:
Introduction, Keywords, Identifiers, White Space
Characters, Comments,
Numbers
Strings
Logic Values
Strengths
Data Types
Scalars and Vectors
Parameters
Operators.
Language Constructs and Conventions
INTRODUCTION :
 The constructs and conventions make up a software language. A clear

understanding and familiarity of these is essential for the mastery of the

language.
 Verilog has its own constructs and conventions .

 Any source file in Verilog (as with any file in any other programming

language) is made up of a number of ASCII characters.

 The characters are grouped into sets — referred to as “lexical tokens.” A

lexical token in Verilog can be a single character or a group of characters.

 Verilog has 7 types of lexical tokens — operators, keywords, identifiers,

white spaces, comments, numbers, and strings.

Contd…
CASE SENSITIVITY :
 Verilog is a case-sensitive language like C.
 Thus case, Case, CASE, cASE,… etc., are all treated as different
entities / quantities in Verilog.

KEYWORDS :

 The keywords define the language constructs. A keyword signifies an

activity to be carried out, initiated, or terminated.

 As such, a programmer cannot use a keyword for any purpose other than

that it is intended for.

 All keywords in Verilog are in small letters.

Contd…
Some of the verilog keyword Examples :
 module signifies the beginning of a module definition.
 endmodulesignifies the end of a module definition.

 begin signifies the beginning of a block of statements.

 end signifies the end of a block of statements.
 if signifies a conditional activity to be checked.
 while signifies a conditional activity to be carried out.
Identifiers :
 Any program requires blocks of statements, signals, etc., to be

identified with an attached nametag. Such nametags are called as

identifiers.
 Examples are clock, enable ……..

 There are some restrictions in assigning identifier names.

 All characters of the alphabet or an underscore can be used as the

first character.
 Subsequent characters can be of alphanumeric type, or the

underscore (_), or the dollar ($) sign.

 for example name, _name. Name, name1, name_$, etc.
Contd…
name aa -- not allowed as an identifier because of the
blank ( “name” and “aa” are interpreted as two
different identifiers)
 $name -- not allowed as an identifier because of the
presence of “$” as the first character.
 1_name -- not allowed as an identifier, since the
numeral “1” is the first character
 @name -- not allowed as an identifier because of the
presence of the character “@”.
 A+b -- not allowed as an identifier because of the
presence of the character “+”.
Contd…
An alternative format makes it is possible to use any of the printable ASCII

characters in an identifier. Such identifiers are called “escaped identifiers”.

they have to start with the backslash (\) character. The character set

between the first backslash character and the first white space
encountered is treated as an identifier.
Examples

 \b=c
 \control-signal
 \&logic
 \abc // Here the combination “abc” forms the identifier.
WHITE SPACE CHARACTERS
 Blanks (\b), tabs (\t), newlines (\n), and form feed form the white

space characters in Verilog.

 In any design description the white space characters are included

to improve readability. Functionally, they separate legal tokens.

 They are introduced between keywords, keyword and an

identifier, between two identifiers, between identifiers and

operator symbols, and so on.
 White space characters have significance only when they appear

inside strings.
COMMENTS
Comments are incorporated in two types :

 A single line comment begins with “//”

Example s:
module d_ff (Q, dp, clk);

//This is the design description of a D flip-flop.

//Here Q is the output.

// dp is the input and clk is the clock.

Contd…
multiline comments “/*” signifies the beginning of a comment

and “*/” its end.

Examples : module d_ff (Q, dp, clk);

/* This module forms the design description of a d_flip_flop

wherein Q is the output of the flip-flop , dp is the data input and clk
the clock input*/
Contd…
Multiline comments cannot be nested. For example, the following

comment is not valid.

/*The following forms the design description of a D flip-flop

/*which can be modified to form other types of flip-flops*/ with

clock and data inputs.*/
A valid alternative can be as follows: -

 /*The following forms the design description of a D flip-flop

(which can be modified to form other types of flip-flops) with

clock and data inputs.*/
NUMBERS
Frequently numbers need to be specified in a design

description.
Logic status of signal lines, buses, delay values, and numbers

to be loaded in registers are examples.

 The numbers can be of two types :

 Integer type
 Real type.
Integer Numbers
Integers are represented in two ways.
In first case, it is a signed or unsigned Decimal number of 32 bits
wide.
Examples are
6
 48
 468
 -582
The invalid representation of Integers are
 8A
 C6
 -4D3
 -5E1
Contd…
The alternate form of number representation is more specific –

though elaborate.
The number can be specified in binary, octal, decimal, or

hexadecimal form.
 The representation has three tokens with an optional sign

preceding it.
Contd…
Contd…
The characters used to specify the base number, the sign or the

magnitude can be in either case (Thus A, B, C, D, E, or F can be

used in place of a, b, c, d, e, or f, respectively, to specify the
concerned hex digit. X or Z can be used in place of x or z value,
respectively).
The single quote character in the base field has to be immediately

followed by the character representing the base. Intervening white

spaces are not allowed. However, such white spaces can precede
the magnitude field.
Contd…
Negative numbers are represented in 2’s complement form.

The question mark character – “?” – can be used in place of z. The

underscore character can be used anywhere after the first character.

It adds to the readability. It is normally ignored.
If the number size is smaller than the size specified, the size is

made up by padding 0’s to the left. However, if the leftmost bit is a

x or z, the same is padded to the left.
Left truncation and right extension can often be confusing. It is

preferable to specify the numbers fully.

Examples

If the number size is smaller than the size specified, the size is made up by padding 0’s to
the left. However, if the leftmost bit is a x or z, the same is padded to the left.
Contd…
Contd…

 If the number size is smaller than the size specified, the size is made up by padding
0’s to the left. However, if the leftmost bit is a x or z, the same is padded to the left.
 Negative numbers are represented in 2’s complement form.
Real Numbers
Real numbers can be specified in decimal or scientific notation.

The decimal notation has the form -a.b

where a, b, the negative sign, and the decimal point have the usual

significance.
The fields a and b must be present in the number.

 A number can be specified in scientific notation as 4.3e2

 where 4.3 is the mantissa and 2 the exponent.
 The decimal equivalent of this number is 430.
Other examples of numbers represented in scientific notation are –

4.3e2, –4.3e–2, and 4.3e–2. The representations are common.

STRINGS :
 A string is a sequence of characters enclosed within double
quotes.
 A string must be contained on a single line; that is, it cannot be
carried over to two lines with a carriage return.
 Special characters are specified by preceding them with the “\”
character.
 Verilog treats a string as a sequence of ASCII characters.
 “This is a string”
 “This string is one \t with a gap in between”
 “This is called a \“string\””.
Contd…
When a string of ASCII characters as above is an operand in an

expression, it is treated as a binary number.

For example, the statement P = “numb”

 assigns the binary value 0110 1110 0111 0101 0110 1101 0110

0010 to P
n - 0110 1110,

u - 0111 0101,
m - 0110 1101 and
b -0110 0010
 Logic Values
1 signifies the 1 or high or true level

0 signifies the 0 or low or false level.

Two additional levels are also possible designated as x and z.

x represents an unknown or an uninitialized value. This

corresponds to the don’t care case in logic circuits.

z represents / signifies a high impedance state. This is possible

when a signal line is tri-stated or left floating

Contd…
 When a variable in an expression is in the z state, the effect is the
same as it having z value.
 But when an input to a gate is in the z state, it is equivalent to
having the x value.
 If the input to a MOS switch is in the z state, its output too remains
at the z state.
 With a few exceptions all data types in Verilog can take on all the 4
logic values or levels.
Contd…
A logic state can have a “strength” associated with it.

 It is a quantitative representation of the internal impedance value

of the corresponding hardware circuit; a change in the internal

impedance is reflected as a corresponding change in the strength
level.
 Whenever the logic values from two sources are combined, there

can be a conflict and the resulting contention has to be resolved.

STRENGTHS
The logic levels are also associated with strengths.

 In many digital circuits, multiple assignments are often combined

to reduce silicon area or to reduce pinouts.

To facilitate this, one can assign strengths to logic levels.

 Verilog has eight strength levels – four of these are of the driving

type, three are of capacitive type and one of the hi-Z type.
When a signal line is driven simultaneously from two sources of

different strength levels, the stronger of the two prevails.

Contd…
Strength Strength Specification Declaration Element Modeled
Name Level Keyword Abbreviation
Supply 7 Supply1 Su1 Power Supply
Drive Supply0 Su0 Connections
Strong 6 Strong1 St1 Default Gate & Assign
Drive Strong0 St0 output strength
Pull Drive 5 Pull1 Pu1 Gate & Assign output
Pull0 Pu0 strength
Large 4 Large1 La1 Size of trireg net
Capacitor Large0 La0 capacitor
Weak 3 Weak1 We1 Gate & Assign output
Capacitor Weak0 We0 strength
Medium 2 Medium1 Me1 Size of trireg net
capacitor Medium0 Me0 capacitor
Small 1 Small1 Sm1 Size of trireg net
Capacitor Small0 Sm0 capacitor
High 0 Highz1 Hi1 Not Applicable
Capacitor Highz0 Hi0
 Contd…
If a signal line a is driven by two sources – b at 1 level with strength
“strong1” and c at level 0 with strength “pull0”– a will take the value 1.
If a signal line a is driven by two sources – b at 1 level with strength
“pull1” and c at level 0 with strength “strong0,” a will take the value 0.
If a signal line a is driven by two sources – b at 1 level with strength
“strong1” and c at level 0 with strength “strong0,” a will take the value x
(indeterminate).
If a signal line a is driven by two sources – b at 1 level with strength
“weak1” and c at level 0 with strength “large0,” a will take the value 0.
DATA TYPES
The data handled in Verilog fall into two categories:
 Net data type
 Variable data type
 The two types differ in the way they are used as well as with
regard to their respective hardware structures.
Data type of each variable or signal has to be declared prior to
its use. The same is valid within the concerned block or
module.
NET DATA TYPE

A net signifies a connection from one circuit unit to another,

which carries the value of the signal it is connected to and
transmits to the circuit blocks connected to it.
If the driving end of a net is left floating, the net goes to the high
impedance state.
A net can be specified in different ways.
wire: It represents a simple wire doing an interconnection. Only
one output is connected to a wire and is driven by that.
tri: It represents a simple signal line as a wire. Unlike the wire,
a tri can be driven by more than one signal outputs.
Contd…
Various nets supported in Verilog
WIRE / TRI WAND / TRIAND

WOR / TRIOR TRI1

TRI0 TRIREG -- Infers a capacitance

SUPPLY1 -- For Vdd SUPPLY0 -- For Vss

Contention
Wire / 0 1 X Z WAND / 0 1 X Z
TRIAND
Tri
0 0 X X 0 0 0 0 0 0
1 X 1 X 1 1 0 1 X 1
X X X X X X 0 X X X
Z 0 1 X Z Z 0 1 X Z

WOR / 0 1 X Z Tri 0 1 X Z
TRIOR
1(0)
0 0 1 X 0
0 0 X X 0
1 1 1 1 1
1 X 1 X 1
X X 1 X X X X X X X
Z 0 1 X Z Z 0 1 X 1 (0)
VARIABLE DATA TYPE
A variable is an abstraction for a storage device.
It can be declared through the keyword reg and stores the value of
a logic level: 0, 1, x, or z.
A net or wire connected to a reg takes on the value stored in the
reg and can be used as input to other circuit elements.
But the output of a circuit cannot be connected to a reg.
The value stored in a reg is changed through a fresh assignment in
the program.
the other variable data types are: time, integer, real, and real
time.
SCALARS AND VECTORS
Entities representing single bits — whether the bit is stored,
changed, or transferred — are called “scalars.”
a group of regs stores a value, which may be assigned, changed, and
handled together are called as a “Vector”

Scalars
and Vectors
Representation
Contd…
Examples:
 wire[3:0] a; /* a is a four bit vector of net type; the bits are
designated as a[3], a[2], a[1] and a[0]. */
 reg[2:0] b; /* b is a three bit vector of reg type; the bits are
designated as b[2], b[1] and b[0]. */
 reg[4:2] c; /* c is a three bit vector of reg type; the bits are
designated as c[4], c[3] and c[2]. */
 wire[-2:2] d ; /* d is a 5 bit vector with individual bits designated
as d[-2], d[-1], d[0], d[1] and d[2]. */
 Contd…
Whenever a range is not specified for a net or a reg, the same is

treated as a scalar – a single bit quantity.

Normally vectors – nets or regs – are treated as unsigned quantities.

They have to be specifically declared as “signed” if so desired.

Examples :
 wire signed[4:0] num; // num is a vector in the range -16 to +15.

 reg signed [3:0] num_1; // num_1 is a vector in the range -8 to +7.

PARAMETERS
In some designs, certain parameter values are not committed at

the outset.
Typical Examples are Proportionality constants, frequency-scaling

levels, number of taps in digital filters, etc.

There are also situations where the size of the design is left open

and decided at a later stage.

Bus width, LIFO depth, and memory size are such quantities

which may be committed later.

Contd…
All such constants can be declared as parameters at the outset in a

Verilog module, and values can be assigned to them;

 Example :
 parameter word_size = 16;

 parameter word_size = 16, mem_size = 256;

The assignment can have algebraic expressions on the right hand

side.
Such expressions can involve constants and other parameters

declared already;
Parameter word_size = 16, factor = word_size/2;
Contd…
However, a parameter that has been assigned a value in a

module definition can have its value changed at runtime – that

is, when the module is used at runtime in some other design
(i.e., instantiated)or when it is tested.
 Such modifications are carried out through a “defparameter”

statement.
OPERATORS
Verilog has a number of operators akin to the C language.

 These are of three types:

 1. Unary: the unary operator is associated with a single operand.

The operator precedes the operand.

Example (Unary) : ~a.

 2. Binary: the binary operator is associated with two operands.

The operator appears between the two operands

Example (Binary) : a&b.
Contd…
3. Ternary: the ternary operator is associated with three operands.

The two operators together constitute a ternary operation. The two

operators separate the three operands.

Example (Ternary) : a?b:c // Here the operators “?” and “:”

together define an operation.