Microprocessor: Pentium
Microprocessor: Pentium
Microprocessor: Pentium
Fourth Generation
During 1980s
Low power version of HMOS technology
(HCMOS)
Third Generation 32 bit processors
During 1978 Physical memory space 224 bytes = 16 Mb
HMOS technology Faster speed, Higher Virtual memory space 240 bytes = 1 Tb
packing density Floating point hardware
16 bit processors 40/ 48/ 64 pins Supports increased number of addressing
Easier to program modes
Dynamically relatable programs
Processor has multiply/ divide arithmetic Intel 80386
hardware
More powerful interrupt handling
capabilities Second Generation
Flexible I/O port addressing During 1973
NMOS technology Faster speed, Higher
Intel 8086 (16 bit processor) density, Compatible with TTL
4 / 8/ 16 bit processors 40 pins
First Generation Ability to address large memory spaces
Between 1971 – 1973 and I/O ports
PMOS technology, non compatible with TTL Greater number of levels of subroutine
4 bit processors 16 pins nesting
8 and 16 bit processors 40 pins Better interrupt handling capabilities
Due to limitations of pins, signals are 1
multiplexed Intel 8085 (8 bit processor)
Microprocessor Functional blocks
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Pins and signals
8086 Microprocessor
Pins and Signals Common signals
AD0-AD15 (Bidirectional)
Address/Data bus
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8086 Microprocessor
Pins and Signals Common signals
MN/ MX
MINIMUM / MAXIMUM
READY
RESET (Input)
CLK
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8086 Microprocessor
Pins and Signals Minimum mode signals
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8086 Microprocessor
Pins and Signals Minimum mode signals
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8086 Microprocessor
Pins and Signals Maximum mode signals
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8086 Microprocessor
Pins and Signals Maximum mode signals
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8086 Microprocessor
Pins and Signals Maximum mode signals
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Architecture
8086 Microprocessor
Architecture
Dedicated Adder to
generate 20 bit address
Segment
Registers
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8086 Microprocessor
Architecture Bus Interface Unit (BIU)
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8086 Microprocessor
Architecture Bus Interface Unit (BIU)
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8086 Microprocessor
Architecture Bus Interface Unit (BIU)
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8086 Microprocessor
Architecture Bus Interface Unit (BIU)
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8086 Microprocessor
Architecture Bus Interface Unit (BIU)
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8086 Microprocessor
Architecture Bus Interface Unit (BIU)
Instruction queue
A group of First-In-First-
Out (FIFO) in which up to
6 bytes of instruction
code are pre fetched
from the memory ahead
of time.
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8086 Microprocessor
Architecture Execution Unit (EU)
EU decodes and
executes instructions.
A decoder in the EU
control system
translates instructions.
and
Some of the 16 bit registers can be
Index registers (Source used as two 8 bit registers as :
Index, Destination Index)
each of 16-bits AX can be used as AH and AL
BX can be used as BH and BL
CX can be used as CH and CL 26
DX can be used as DH and DL
8086 Microprocessor
Architecture Execution Unit (EU)
AL in this case contains the low order byte of the word, and
AH contains the high-order byte.
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8086 Microprocessor
Architecture Execution Unit (EU)
Auxiliary Carry Flag
Carry Flag
Flag Register This is set, if there is a carry from the
This flag is set, when there is
lowest nibble, i.e, bit three during
addition, or borrow for the lowest a carry out of MSB in case of
nibble, i.e, bit three, during addition or a borrow in case
subtraction. of subtraction.
This flag is set, when the This flag is set, if the result of This flag is set to 1, if the lower
result of any computation the computation or comparison byte of the result contains even
is negative performed by an instruction is number of 1’s ; for odd number
zero of 1’s set to zero.
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OF DF IF TF SF ZF AF PF CF
Tarp Flag
Over flow Flag If this flag is set, the processor
This flag is set, if an overflow occurs, i.e, if the result of a signed
enters the single step execution
operation is large enough to accommodate in a destination
mode by generating internal
register. The result is of more than 7-bits in size in case of 8-bit
signed operation and more than 15-bits in size in case of 16-bit interrupts after the execution of
sign operations, then the overflow will be set. each instruction
8086 registers
categorized 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
into 4 groups OF DF IF TF SF ZF AF PF CF
1. Register Addressing
Group I : Addressing modes for
2. Immediate Addressing register and immediate data
3. Direct Addressing
5. Based Addressing
Group II : Addressing modes for
6. Indexed Addressing memory data
7. Based Index Addressing
8. String Addressing
8. String Addressing
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8086 Microprocessor Group I : Addressing modes for
Addressing Modes register and immediate data
1. Register Addressing
In immediate addressing mode, an 8-bit or 16-bit
2. Immediate Addressing data is specified as part of the instruction
3. Direct Addressing
Example:
4. Register Indirect Addressing
MOV DL, 08H
5. Based Addressing
The 8-bit data (08H) given in the instruction is
6. Indexed Addressing moved to DL
8. String Addressing
MOV AX, 0A9FH
9. Direct I/O port Addressing
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8086 Microprocessor
Addressing Modes : Memory Access
Supported combinations:
BX SI
+ disp
BP DI 37
8086 Microprocessor Group II : Addressing modes
Addressing Modes for memory data
1. Register Addressing
2. Immediate Addressing
Here, the effective address of the memory
3. Direct Addressing
location at which the data operand is stored is
4. Register Indirect Addressing given in the instruction.
12. Implied Addressing This addressing mode is called direct because the
displacement of the operand from the segment
base is specified directly in the instruction.
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8086 Microprocessor Group II : Addressing modes
Addressing Modes for memory data
(CL) (MA)
(CH) (MA +1)
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8086 Microprocessor Group II : Addressing modes
Addressing Modes for memory data
(AL) (MA) 40
(AH) (MA + 1)
8086 Microprocessor Group II : Addressing modes
Addressing Modes for memory data
(CL) (MA)
(CH) (MA + 1)
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8086 Microprocessor Group II : Addressing modes
Addressing Modes for memory data
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8086 Microprocessor Group II : Addressing modes
Addressing Modes for memory data
1. Register Addressing
2. Immediate Addressing
8. String Addressing
000AH 0AH (sign extend)
1. Register Addressing
2. Immediate Addressing
3. Direct Addressing
5. Based Addressing
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