APE370: Microprocessor,

Micro-Controller and
Computer Peripherals

WELCOME
A.T.M. SAIFUL ISLAM
Lecturer
Department of APECE
BSMRSTU
 Chapter 1:
Microprocessors
Microprocessor:
A microprocessor is a multipurpose, programmable, clock-driven, register-
based electronic device that reads binary instructions from a storage device
called memory, accept binary data as input and processes data according to
those instructions and provide results as output.

Applications:
A micro processor can be embedded in a larger system, can be a stand
alone unit controlling processes, or it can function as the CPU of a
computer called a microcomputer.
 Evaluation of Microprocessors (Intel Family):

Figure 1.1: The Z3 (1930s) computer developed by Konrad Zuse uses a 5.33 hertz
clocking frequency.
Intel 4004:

 The world’s first microprocessor

 4-bit microprocessor
 Programmable controller on a chip
 4K nibbles address space
 45 instructions
 P-channel MOSFET technology
 Instruction execution rate of 50 KIPs

Intel 8008:

 Later in 1971
 8-bit version of the 4004 microprocessor
 16K bytes memory space
 A total of 48 instructions
Intel 8080:

 In 1973
 8-bit microprocessors
 After 6 months later Motorola Corporation introduced MC6800
microprocessor
 64K bytes memory space
 10 times faster than the 8008

Intel 8085:

 In 1977
 8-bit microprocessors
 Higher speed (1.3 μs) than 8080 (2 μs)
 Low cost compare to 8080
The Modern Microprocessor (8086/8088):

 In 1978, Intel released the 8086 microprocessor

 A year or so later, it released the 8088
 16-bit microprocessor
 1M byte of memory
 High speed (2.5 MIPs)
Register and accumulator based microprocessor:
 Microprocessors having Accumulator and Registers.
 Register is a small amount of storage available as part of a
processor.
 Such registers can be accessed much faster than main memory.
 Accumulator is a register in which intermediate arithmetic and
logical results are stored.
 With out register like accumulator, result of each calculation
need to stored in main memory.
 Accumulator is much and much faster than main memory.
 Microprocessor as the CPU of microcomputers:
CPU

Arithmetic/
Logic Unit
Micro-
(ALU)
processor
As
CPU
Input Control Unit Output Input Output

Memory Memory

(a) (b)
Figure 1.2: (a) Block diagram of a computer system, (b) Block diagram of a
Computer with the Microprocessor as CPU
 A computer system has four components: memory, input, output
and the central processing unit (CPU).
 CPU consists of the arithmetic/logic (ALU) and control unit.
 CPU contains various registers to store data temporarily.
 In late 1960s CPU was designed with discrete component.
 CPU on a single chip come to be known as a microprocessor.
 Microprocessor is a primary component of a computer system.
 A computer with a microprocessor as its CPU is known as
microcomputer.
 MPU implies a complete processing unit with the necessary
control signals.
Basic Microprocessor types:
 Basically two types
 General Purpose and single chip microprocessors
 Bit slice microprocessor
General Purpose and single chip microprocessor:
 Designed in a single chip.
 Typically 256 bytes of R/W memory.
 1K to 8K bytes of ROM.
 Several single lines to connect I/Os.
 Complete microcomputers on a chip.
 Also known as microcontroller.

Bit slice microprocessor:

 A microprocessor designed to allow variable word sizes using 2, 4, or 8
bit processor units on a single chip.
 These devices can be paralleled to yield an 8, 12, 16, 24, 32 or 64 bit
processor.
 Faster operation.
 Chapter 2:
8086 Microprocessor
Internal architecture of 8086 microprocessor:

Figure 2.1: Internal architecture of 8086 microprocessor.

 The 8086 CPU is organized as two separate processors, called the Bus
Interface Unit (BIU) and the Execution Unit (EU).
 BIU (Bus Interface Unit):
 Generate the memory and I/O addresses.
 Send out tasks to EU.
 Fetch instructions from memory.
 Read data from memory and ports.
 Write data to memory and ports.
 BIU takes care of all the address and data transfers on the buses.
 EU (Execution Unit):
 Inform BIU, from where to fetch the instruction or data.
 Receive instruction codes and data from the BIU
 Decode and execute the fetched instructions.
 Store the results in the general registers
 EU has no direct connection to system bus, it receives and outputs all
its data through the BIU.
 EU takes care of performing operations on data.
Instruction fetch and execute:
1. The BIU outputs the contents of the instruction pointer register (IP) onto the
address bus, causing the selected byte or word to be read into the BIU.
2. Register IP is incremented by 1 to prepare for the next instruction fetch.
3. Once inside the BIU, the instruction is passed to the “queue”. This is a first-
in, first-out storage register sometimes likened to a “pipeline”.
4. Assuming that the queue is initially empty, the EU immediately draws this
instruction from the queue and begins execution.
5. While the EU is executing this instruction, the BIU proceeds to fetch a new
instruction. Depending on the execution time of the first instruction, the BIU
may fill the queue with several new instructions before the EU is ready to
draw its next instruction.

 EU can execute instructions almost continually instead of having to wait for

the BIU to fetch a new instruction.
 Slow memory parts can be used without affecting overall system
performance.
 Power
Supply
Vcc GND
Address/
Data bus
AD0-AD15,
INTR
A16/S3-A19/S6
Interrupt INTA
Interface TEST
ALE
NMI
BHE/S7
RESET
8086 M/IO
MPU DT/R Memory/IO
DMA HOLD
Interface HLDA RD
Control

WR

Mode DEN
select NM/MX
READY

(a) (b)
Figure 2.2: (a) Pin architecture, (b) Minimum mode block diagram, of
8086.
 Vcc 5V
Power
Supply GND Ground

INTR Interrupt request

INTA Interrupt acknowledge
Interrupt
TEST Wait and test control
Interface
NMI Non-maskable Interrupt request
RESET System reset
DMA HOLD Hold request
Interface HLDA Hold acknowledge
Mode select NM/MX Maximum/Minimum mode control
Signals of
8086 micro Address/ AD0-AD15 Address/data bus
processor Data bus A16/S3-A19/S6 Address/Status
ALE Address letch enable
M/IO Memory/IO control
DT/R Data transmit/receive
RD Read control
Memory/IO WR Write control
Control DEN Data enable
READY Wait state control

BHE Bank high enable

8086 Programming model:

16 bits 88 bits
bits
Flags Register
AX CS
16 bits
AH AL IP
15 O D I T S Z A P C0
SS
BX O = Overflow
SP
BH BL D = Direction
BP I = Interrupt
CX SI T = Trace
CH CL S = Sign
DI Z = Zero
DX DS A = Auxiliary Carry
ED P = Parity
DH BL C = Carry

Figure 2.3: The programming model of the 8086

 AH, AL, BH, BL, CH, CL, DH, and DL are 8-bit registers.
 AX, BX, CX, DX, SP, BP, DI, SI, IP, FLAGS, CS, DS, ES, and SS
are 16 bit registers (User accessible registers).
 First four 16 bit registers contain a pair of 8-bit registers.
 Some registers are general-purpose or multipurpose while some
have special purposes.
 AX, BX, CX, DX, BP, DI, SI are multipurpose registers, are used
for almost any purpose as dictated by a program.
 SP, IP, FLAGS are special-purpose registers.
 CS, DS, ES, and SS are segment registers.
Multipurpose Registers:

 AX (accumulator): AX is referenced as a 16-bit register (AX), or as

either of two 8-bit registers (AH and AL). In general, accumulator holds
the result.
 BX (base index): The BX register sometimes holds the offset address
of a memory location.
 CX (counter): That holds the count for various instructions.
 DX (data): That holds a part of the result from a multiplication or part
of the dividend before a division.
 BP (base pointer): BP points to a memory location of the
microprocessor for memory data transfers.
 DI (destination index): DI often addresses string destination data for
the string instructions.
 SI (source index): Used to addresses source string data for the string
instructions.
Special-Purpose Registers:
 IP (instruction pointer): IP points to the next instruction in a
program. The instruction pointer can be modified with a jump or a call
instruction.
 SP (stack pointer): SP addresses an area of memory called the stack.
 FLAGS: FLAGS indicate the condition of the microprocessor and
control its operation.
 C (carry): Hold carry after addition or the borrow after
subtraction.
 P (parity): Parity is a logic 0 for odd parity and a logic 1 for even
parity.
 A (auxiliary carry): It holds the carry (half-carry) after addition
or the borrow after subtraction between bit positions 3 and 4 of
the result.
 Z (zero): If Z=1, the result (arithmetic or logic operation) is zero;
if Z=0, the result is not zero.
 S (sign): S=1 if the result is negative and S=0 if the result is
positive.
 T (trap): If T=1, the microprocessor interrupts the flow of the
program on conditions as indicated by the debug registers and
control registers. If the T=0 the debugging feature is disabled.
 I (interrupt): If I=1, INTR pin is enabled; if I=0, the INTR pin is
disabled.
 D (direction): If D=1, the DI and/or SI registers are automatically
decremented; if D=0, the DI and/or SI registers are automatically
incremented.
 O (overflow): An overflow (O=1) indicates that the result has
exceeded the capacity of the machine.
Segment Registers:

 CS (code): CS is a section of memory that holds the code used by

the microprocessor.
 DS (data): The DS is a section of memory that contains most data
used by a program.
 ES (extra): The ES is an additional data segment that is used by
some of the string instructions to hold destination data.
 SS (stack): The stack segment defines the area of memory used for
the stack.
 T-state: One sub-division of an operation performed in one clock
cycle is called a T-state. T1, T2, T3, T4 etc are called T states.
 Machine cycle: A group of state come together to perform one
operation is called machine cycle.
 Instruction cycle: The total time for fetching and executing an
instruction is called instruction cycle. An instruction cycle consists of
one or more machine cycle.

T1 T2 T3 T1 T2 T3 T4

Clock

Operation

Instruction

Figure 2.4: Timing diagram of an instruction.

Timing diagram of Memory read machine cycle:
Instruc-tion Memory read/Opcode fetch
T-state T1 T2 T3 T4

CLK

A19/A16-S6/S3 A19-A16 S7-S3

AD15-AD0 A15-A0 Data In

M/IO

ALE

DT/R

RD

DEN

READY
Timing diagram of Memory write machine cycle:
Instruction Memory write
T-state T1 T2 T3 T4

CLK

A19/A16-S6/S3 A19-A16 S7-S3

AD15-AD0 AD15-AD0 Data from MPU

M/IO

ALE

DT/R

WR

DEN

READY
Stack memory:

 The stack plays an important role in all microprocessors.

 It holds data temporarily and stores the return addresses.
 The stack memory is an LIFO (last-in, first-out) memory.
 Data are placed onto the stack with a PUSH instruction and retrieved
with a POP instruction.
 The CALL instruction also uses the stack to hold the return address.
 A RET (return) instruction to retrieve the return address from the
stack.
 The stack memory is maintained by two registers: the stack pointer
(SP or ESP) and the stack segment register (SS).
Subroutine:

 An important part of any computer system’s architecture.

 A subroutine is a group of instructions that usually performs one task.
 A subroutine is a reusable section of the software that is stored in
memory once, but used as often as necessary.
 This saves memory space and makes it easier to develop software.
 The only disadvantage of a subroutine is that it takes the computer a
small amount of time to link to the procedure and return from it.
 The CALL instruction links to the subroutine, and the RET (return)
instruction returns from it.
 The stack stores the return address whenever a subroutine is called
during the execution of a program.
Interrupt:
An interrupt is either a hardware-generated CALL (externally derived from
a hardware signal) or a software-generated CALL (internally derived)
instruction to execute a interrupt service routines.
Interrupt types:
 Non-maskable interrupt (NMI): It requires an immediate response by
microprocessor, it usually used for serious circumstances like power
failure.
 Maskable interrupt (INTR): It is an interrupt that the microprocessor
can ignore depending upon some predetermined condition defined by
status register.
 Hardware interrupt : The primary sources of interrupts, sources are the
PCs timer chip, keyboard, serial ports, parallel ports, disk drives,
CMOS real-time clock, mouse, sound cards, and other peripheral
devices.
 Software interrupt: The source of the interrupt is the software program.
Software Interrupt instructions can be used to test the working of the
various Interrupt handlers.
Interrupt process of the 8086 Microprocessor:
 External interface sends an interrupt signal, to the INTR pin, or an
internal interrupt occurs.
 The CPU finishes the present instruction (for a hardware interrupt)
and sends Interrupt Acknowledge (INTA) to hardware interface.
 The interrupt type N is sent to the Central Processor Unit (CPU) via
the Data bus from the hardware interface.
 The contents of the flag registers are pushed onto the stack.
 Both the interrupt (IF) and (TF) flags are cleared. This disables the
INTR pin and the trap.
 The contents of the code segment register (CS) and instruction
pointer (IP) are pushed onto the Stack.
 The interrupt vector contents are fetched, from (4 x N) and then
placed into the IP and from (4 x N +2) into the CS.
 Execute the interrupt service routine.
 Returning from the interrupt-service routine by the IRET instruction,
the IP, CS and Flag registers are popped from the Stack.
Addressing modes of 8086 microprocessor:
The data-addressing modes of 8086 microprocessor include register,
immediate, direct, register indirect, base-plus index, register-relative, and
base relative-plus-index addressing.
 Register addressing: Register addressing transfers a copy of a byte or
word from the source register or contents of a memory location to the
destination register or memory location. Example: MOV CX, DX.
 Immediate addressing: Immediate addressing transfers an immediate
data, into the destination register or memory location. Example: MOV
AL, 22H.
 Direct addressing: Direct addressing moves a byte or word between a
memory location and a register. The instruction set does not support a
memory to memory transfer, except with the MOVS instruction. MOV
[1234H], AX.
 Register indirect addressing: Register indirect addressing transfers a
byte or word between a register and a memory location, addressed by an
index or base register (BP, BX, DI, and SI). Example: MOV AX, [BX].
 Base-plus index addressing: Base-plus-index addressing transfers a
byte or word between a register and the memory location addressed
by a base register (BP or BX) plus an index register (DI or SI).
Example: MOV [BX+DI], CL.
 Register-relative addressing: Register relative addressing moves a
byte or word between a register and the memory location addressed
by an index or base register plus a displacement. Example: MOV AX,
[BX+4].
 Base relative-plus-index addressing: Base relative-plus-index
addressing transfers a byte or word between a index register and the
memory location addressed by a base and an index register plus a
displacement. Example: MOV AX, [BX+DI+4].
 Memory management of 8086 microprocessor:
 The 8086 divides its 1 MB of memory FFFFF
MEMORY

address space into data, code, stack, and

extra segments.
59000
 The segment registers DS, CS, SS, and ES 68FFF
point to beginning address of any 64K-byte 49000
EXTRA ES
current memory segment. 48FFF

 In this example, the stack and extra segments 44000

43FFF SS
are partially overlapped. STACK
34000
 The offset address selects any location within 33FFF

the 64K byte memory segment. 30000

2FFFF
 Each segment register is internally appended CODE CS
with a 0H on its rightmost end, this forms a 20000
1FFFF
20-bit memory address.
DATA DS
 If a segment address is 1000 and offset 10000
address is 2000 then the real address will be 0FFFF

12000.
00000

Figure 2.5: Placement of four memory segments in a memory system.

 Chapter 3:
Advanced Microprocessors
Overview:
In 1978, Intel released the 8086 microprocessor; a year or so later, it
released the 8088. Both devices are 16-bit microprocessors with 1MB
memory space and the execution speed of these microprocessor was 2.5
MIPs.

 Intel 80186 microprocessor:

 16-bit microprocessor.
 It contain additional reserved interrupt vectors and some very
powerful built-in I/O features.
 The 80186 often called embedded controllers because of their
application as a controller.
 Intel 80286 microprocessor:
 16-bit architecture microprocessor.
 It can address a 16M-byte memory system.
 It has few additional instructions than 8086 that managed the
extra 15M bytes of memory.
 It has the execution speed of 4.0 MIPs
 Intel 80386 microprocessor:
 Invented in 1986.
 Intel’s first practical 32-bits microprocessor.
 It can address up to 4G bytes of memory.
 Useful for the systems that use a GUI (Graphical User Interface)
also useful for CAD system.
 Intel 80486 microprocessor:
 Released in 1989.
 32 bit microprocessor.
 The execution speed (50MHz) was twice of 80386.
 Intel pentium microprocessor:
 Released in 1993.
 32 bit microprocessor.
 16K-byte of cache memory.
 Operated in three different speed clocking frequency of 60MHz,
66MHz and 100MHz.
 The double-clocked Pentium, operating at 120 MHz and 133 MHz
 Internal architecture and programming model of 80186/80286
microprocessor:
 See the internal architecture and programming model of 8086
microprocessor.
Flags register of 80286 microprocessor:
Flags Register
16 bits
IOP IOP
15 NT 1 0 O D I T S Z A P C 0

NT = Nested task, IOPL = I/O privilege level, O = Overflow, D = Direction, I

= Interrupt, T = Trace, S = Sign, Z = Zero, A = Auxiliary Carry, P = Parity, C =
Carry
 IOPL (I/O privilege level): It is used in protected mode operation to select
the privilege level (00 is highest and 11 is lowest) for I/O devices. If the
IOPL is lower than the current privilege level, an interrupt occurs, causing
execution to suspend.
 NT (nested task): NT = 1, indicates that the current task is nested within
another task in protected mode operation.
Internal architecture of 80386/80486 microprocessor:

EAX
EBX FS
ECX GS
EDX
ESP
EBP
ESI
EDI

Figure 3.1: Internal architecture of 80386/80486 microprocessor.

Programming model of 80386/80486 microprocessor:

Flags register

80386
80486

AC = Alignment check. D = Direction.

VM = Virtual mode. I = Interrupt.
RF = Resume. T = Trace.
NT = Nested task. S = Sign.
IOPL = I/O privilege level. Z = Zero.
A = Auxiliary Carry. P = Parity.
O = Overflow. C = Carry.

Figure 3.2: The programming model of the 80386/80486.

 FS and GS: The FS and GS segments are supplemental segment
registers. They are used to addressed two additional memory
segments. Windows uses these segments for internal operations.

 EFLAGS:
 RF (resume): The resume flag is used with debugging to
control the resumption of execution after the next instruction.
 VM (virtual mode): VM flag bit selects virtual mode operation
in a protected mode system. A virtual mode system allows
multiple DOS memory partitions to coexist in the memory
system.
 AC (alignment check): The alignment check flag bit activates if a
word or double-word is addressed on a non-word or non-double-word
boundary.
Overview of Pentium processor:
 The Pentium, introduced in 1993.
 64 bit microprocessor.
 16K bytes cache memory.
 Two introductory versions of the Pentium operated with a clocking
frequency of 60 MHz and 66 MHz.
 The double-clocked Pentium, operating at 120 MHz and 133 MHz.
 A dual integer processor often allows two instructions per clock.
 Pentium allow full-frame video displays to operate at scan rates of
30 Hz or higher comparable to commercial television.
 Pentium also employs an internal floating-point coprocessor to
handle floating-point data.
Co-processor:
A special-purpose processing unit that assists the CPU in performing certain
types of operations more quickly than the basic microprocessor circuits
could perform the same task. For example, a math coprocessor performs
mathematical computations, particularly floating point operations.
 Program itself must be written to take advantage of the coprocessor.
 Mostly math coprocessor, numeric coprocessor, or floating point
coprocessors are built-in.
 High-end graphics, broadband signal processing and encryption/
decryption are designed as separated co-processor.
 Coprocessors cannot fetch instructions from memory, execute program
flow control instructions, do I/O operations, manage memory, and so
on.
 The coprocessor requires the host processor to fetch the coprocessor
instructions and handle all other operations aside from the coprocessor
functions.
Alpha processor:
Alpha, originally known as Alpha AXP, is a 64-bit reduced instruction set
computing (RISC) instruction set developed by Digital Equipment
Corporation (DEC). Alpha was implemented in microprocessors originally
developed and fabricated by DEC. These microprocessors are called alpha
processor, were most prominently used in a variety of DEC workstations
and servers.
 All registers are 64 bits in length.
 32 integer registers and 32 floating point registers.
 31th Integer and floating point registers are used for null operations.
 There are no instructions that operate directly on values stored in
memory, all data manipulation is done between registers.
 In Alpha AXP the generate flags is not stored in a processor status
register, but is instead stored in a third register.
 Instructions on unrelated registers do not have to wait for each other to
execute as they would if there were a single status register.
Pipeline processor:
In computers, a pipeline is the continuous and somewhat overlapped
movement of instruction to the processor or in the arithmetic steps taken
by the processor to perform an instruction.
Let us break down our microprocessor into 5 distinct activities, which
generally correspond to 5 distinct pieces of hardware:

1. Instruction fetch (IF)

2. Instruction Decode (ID)
3. Execution (EX)
4. Memory Read/Write (MEM)
5. Result Write back (WB)
Figure 3.3: Typical Instruction execution
steps in a processor.

 Without pipelining, a computer processor need to process the

instructions one by one.
 While fetching instruction, the arithmetic part of the processor is idle,
it must wait until the next instruction.
 With pipelining, it is possible to fetch next instruction while the
processor is performing arithmetic or other operations.
Clock cycle
Instruction No.

Figure 3.4: Pipelining process in a typical pipelining processor.

 Advantages of pipelining:
 Pipelining can faster the whole process with out increasing
clock frequency or reducing latency.
 Increase the instruction throughput.
 Pipelined CPUs generally work at a higher clock frequency than
the RAM clock frequency.
 Increasing computers overall performance.
 Disadvantages:
 Non-pipelined processor simpler and cheaper to manufacture.
 High pipelining leads to increase of latency.
 A pipelined system typically requires more circuit elements,
processing units, computer memory, etc.
 Branching instruction lower the performance of a long pipelined
processor.
 Dependent instruction execution is much slower (waiting for
first stage output) in pipelined processor.
 Chapter 4:
Assembly Language
Introduction to IBM PC assembly language:

 An assembly language program consists of statements.

 Only one statement is written per line.
 Each statement is either an instruction or an assembler directive.
 Instruction is translated into machine code.
 Assembler directive instructs the assembler to perform some specific
task.

Instruction format:

The general format for an assembly language program statement is as

follows:

operation operand’(s) comment

Examples: MOV CX,5 ; initialize counter
Assembly instruction types:

 Data transfer instruction

 Arithmetic and Logic instruction
 Program control instruction
Data transfer instruction:
 Used to move data from one memory/register to another
memory/register.
 Data transfer instructions include MOV, MOVSX, MOVZX,
PUSH, POP, BSWAP, XCHG, XLAT, IN, OUT, XCHG
 Examples:
 MOV BX,CS
 XCHG BX, CX
 MOV BH, 18H
 MOV CL, [12586H]
Arithmetic and Logic instruction:

 Used for different arithmetic operations and different logical

operations on data.
 Arithmetic instructions include addition, subtraction, multiplication,
division, comparison, negation, increment, and Decrement.
 Logical instructions include AND, OR, Exclusive-OR, NOT, shifts,
rotates, and the logical compare (TEST).

 Examples:
 ADD BX,CS
 SUB BH, 18H
 INC BL
 AND BX, CS
 CMP CL,BL
 SHR BX,12
 Program control instruction:
 Used for controlling different program conditions.
 Program control instruction include JMP, JZ, JNZ, JC, JNC, JCXZ,
JNP etc.
 Examples:
 JMP Start
 JNZ Test
 JC Carry
String processing:
 There are five string data transfer instructions: LODS, STOS, MOVS, INS, and
OUTS.
 Each string instruction allows data transfers that are either a single byte, word,
or double-word (or if repeated, a block of bytes, words, or double-words).
 Examples:
 MOVSB ES:[DI] = DS:[SI]; DI = DI ± 1; SI = SI ± 1
 End at CX=0
Procedures
 Avoid writing the same sequence of instruction again and again.
 Write it in a separate subprogram and call that subprogram (By
using CALL instruction) whenever necessary.
 A big advantage of using procedures is that the machine codes of
procedures needs to be loaded in to main memory only once.
 Procedures slower the execution speed.
 Format
procedure_name PROC
Body of procedure
RET
ENDP procedure_name
 Example
Dcopy PROC
MOV AL, data1
MOV AH, data2
RET
ENDP Dcopy
 Invocation
...
CALL Dcopy
...
Macro:
 A macro is the group of instruction we bracket and give a name to at the start of
the program.
 Using macro avoids the overhead time involved in calling and returning from a
procedures.
 Disadvantage is that this will make the program take up more memory than using
a procedure.
 Macros can be defined with MACRO and ENDM.
 Format
macro_name MACRO [parameter1, parameter2, ...]
macro body
ENDM
 Example
Axchg MACRO operand1, operand2
xchg AL,operand1
xchg AH,operand2
ENDM
 Invocation
...
BX,27H
Axchg
...
Virtual memory management:
 The 80286 microprocessor is an advanced version of the 8086
microprocessor that was designed for multiuser and multitasking
environments.
 The 80286 addresses 16M bytes of physical memory and 1G bytes of virtual
memory by using its memory-management system.
 It allows a very large system to execute in smaller physical memory systems.
 Addressing a 1G-byte memory system is accomplished by the descriptors in
the 80286 microprocessor.
 Each 80286 descriptor describes a 64K-byte memory segment and the 80286
allows 16K descriptors.
 This (64K × 16K) allows a maximum of 1G bytes of memory to be described
for the system.
 In virtual mode CS selects a descriptor that describes the starting address and
length of a section of memory holding code.
 The code segment is limited to 64K bytes in the 8088–80286, and 4G bytes in
the 80386 and above.
Cache memory:
 Cache memory, also called CPU memory, is random access memory that a
computer microprocessor can access more quickly than it can access regular
RAM. 
 As the microprocessor processes data, it looks first in the cache memory and
if it finds the data there (from a previous reading of data), it does not have to
do the more time-consuming reading of data from larger memory. 
 Cache memory is fast and it is expensive. It is categorized in levels that
describe its closeness and accessibility to the microprocessor.
 Level 1 (L1) cache, which is extremely fast but relatively small, is located
close to the processor. 
 Level 2 (L2) cache is located half-way between the process and the system
bus; it is fairly fast and medium-sized.
 Level 3 (L3) cache is relatively large and close to RAM. 
Exception/Interrupt handler:
 Chapter 6:
Computer Peripherals
HDD:
 A hard disk drive (HDD) is a data
storage device used for storing and
retrieving digital information using
rapidly rotating disks (platters)
coated with magnetic material.
 An HDD retains its data even
when powered off.
 Data is read in a random access
manner, meaning individual blocks
of data can be stored or retrieved
in any order rather than
sequentially.

 An HDD consists of one or more rigid ("hard") rapidly rotating disks

with magnetic heads arranged on a moving acuator arm to read and
write data to the surfaces.
HDD:
 The primary characteristics of an HDD are its capacity and
performance.
 Typically, some of an HDD's capacity is unavailable to the user
because it is used by the file system and the computer operating
system, and possibly inbuilt redundancy for error correction and
recovery.
 Performance is specified by the time to move the heads to a file
(average access time) plus the time it takes for the file to move under
its head (average latancy.
 An HDD records data by magnetizing a thin film of ferromagnetic
material on a disk.
 Sequential changes in the direction of magnetization represent binary
data bits.
 The data is read from the disk by detecting the transitions in
magnetization. User data is encoded using an encoding scheme.
FDD:
USB:
 Universal Serial Bus (USB) is an
industry standard developed in the
mid-1990s.
 UBS defines the cables, connectors
and communications protocols used
in a bus for connection,
communication, and power supply
between computers and electronic
devices.
 USB was designed to standardize
the connection of computer
peripherals (including keyboards,
pointing devices, digital cameras,
printers, portable media players,
disc drives etc.

 USB has effectively replaced a variety of earlier interfaces, such as serial

and parallel ports, as well as separate power chargers for portable devices.
WHAT IS A PRINTER?
 An external hardware device responsible for taking
computer data and generating a hard copy of that data.
Printers are one of the most commonly used peripherals
and they print text and still images on the paper.

62
“DOT MATRIX PRINTER”
 The term dot matrix refers to
the process of placing dots to
form an image.
 Its speed is usually 30 to 550
characters per second (cps).
 This is the cheapest and the
most noisy printer and has a
low print quality. Dot Matrix
were 1st introduced by
Centronics in 1970.

63
 HOW DOT-MATRIX WORKS?
 The dot matrix forms images one character at a time
as the print head moves across the paper.
 Uses tiny pins to hit an ink ribbon and the paper
much as a typewriter does.
 This printer arranges dots to form characters and all
kinds of images.
 9 to 24 vertical column pins are contained in a
rectangular print head. When print head moves across
the paper, pins are activated to form a dotted
character image. These printers can produce carbon
copies along with the originals.
64
“A TYPICAL DOT MATRIX OUTPUT”

65
“ADVANTAGES/DIS-ADVATAGES
OF DOT-MATRIX”
 Advantages:
 (1) In-expensive.
 (2) Low per page cost.
 (3) Energy efficient.
 Dis-advantages:
 (1) Noisy
 (2) Low resolution
 (3) Limited fonts flexibility
 (4) Poor quality graphics output.

66
“LASER PRINTER”
 Laser printers use very
advanced technology and
produce a high quality
output. Laser printers can
also produce high quality
graphics images.
 Resolution is 600 to
1200dpi.
67
 HOW LASER PRINTER WORKS?
 (1) Paper is fed and the drum rotates.
 (2) A laser beam conveys information from the
computer to a rotating mirror and thus an image
is created on the drum.
 (3)The charges on the drum are ionized and the
toner sticks to the drum.
 (4)Toner is transferred from drum to paper.
 (5)Heat is applied to fuse the toner on the paper.

68
“INK-JET PRINTER”
 Itis a non-impact printer
producing a high quality
print. A standard Inkjet
printer has a resolution of
300dpi. Newer models have
further improved dpi. Inkjet
printers were introduced in
the later half of 1980s and
are very popular owing to
their extra-ordinary
performance.
69
 HOW INKJET PRINTER WORKS?
 (1) Print head having four ink
cartridges moves .
 (2) Software instructs where to apply
dots of ink, which color and what
quantity to use.
 (3) Electrical pulses are sent to the
resistors behind each nozzle.
 (4) Vapor bubbles of ink are formed by
resistors and the ink is forced to the
paper through nozzles.
 (5) A matrix of dots forms characters Color cartridge showing inkjet nozzles.

and pictures.
70
Digital display:
Motherboard:
 Chapter 5:
Microcontrollers
Microcontroller:
An embedded microcontroller is a chip which a computer processor with
all it’s support functions (clocking and reset), memory, and i/O built into
the device.

Power dist Control store

Processor

I/O ports
Reset control

Clock and
timing RAM

Microcontroller block diagram

Types of microcontrollers:
Embedded
 All the hardware required to run the application is provided on the
chip.
 Typically: power, reset, clock, memory and IO.
External memory
 Some microcontrollers allow the connection of an external
memory
Comparison between microcontroller and microprocessor:

Microcontroller seems to primarily differ from a microprocessor in the

areas of built-in peripheral features. These features could include memory
device selection, timers, interrupt controllers, DMA, and IO devices like
serial ports.
 Microprocessor Microcontroller
Memory and I/O components have to be Micro controller has external processor along
connected externally, the circuit becomes with internal memory and i/O components, the
large. circuit is small.
Cannot be used in compact systems and hence Can be used in compact systems and hence it
inefficient, cost of the entire system increases
is an efficient technique and low cost.
Since external components are low, total
Entire power consumption is high. Hence it is
power consumption is less and can be used
not suitable to used with devices running on
with devices running on stored power like
stored power like batteries.
batteries.
Since memory and I/O components are
Since components are internal, most of
all external, each instruction will need
the operations are internal instruction,
external operation, hence it is relatively
hence speed is fast.
slower.
Microprocessor have less number of Micro controller have more number of
registers, hence more operations are registers, hence the programs are easier
memory based. to write.
Used mainly in washing machine, MP3
Mainly used in personal computers
players
Microcontroller of different manufacturers:
Princeton:
 US govt asked for computer to be used with naval shell distance
for varying elevations and environmental conditions.
 Princeton provided ‘Von Neumann’ architecture where common
memory space are used for storing program and data.
 Memory unit is responsible for arbitrary access to memory space
between reading instructions and passing data back and forth with
processor and its internal registers.
 Advantages: simple memory interfacing and management.
 Example: Intel® Microcontrollers.
Harvard:
 Harvard proposes a design that used separate memory banks for
program storage, the processor stack, and variable RAM.
 Advantage: execute instruction in fewer cycles than Von
Neumann.
 Example: PIC microcontroller.
 instruction
program decode
ROM
Data
memory
Variable Processor and
Addr interface
RAM built-in registers
unit
Stack RAM Ctrl

Princeton architecture block diagram

Data
Addr instruction
Ctrl decode

program PC Stack Variable

ROM RAM
Processor and Data
built-in Addr
registers
Ctrl

Harvard architecture block diagram

Features of PIC16F84 microcontroller:
 PIC16F84 belongs to a class of 8-bit microcontrollers of RISC
architecture.
 Since PIC16F84 is a RISC microcontroller, that means that it has a
reduced set of instructions, more precisely 35 instructions.
 All of these instructions are executed in one cycle except for jump and
branch instructions.
 Operating speed: 10 MHz
 Program Memory: 1 K Flash
 Data RAM: 68 bytes.
 15 special function hardware registers.
 Direct, indirect and relative addressing modes.
 Four interrupt sources.
 1000 erase/write cycles Flash program memory.
 10,000,000 erase/write cycles EEPROM data memory.
 EEPROM Data Retention > 40 years.
 13 I/O pins with individual direction control.
 8-bit timer/counter with 8-bit programmable prescaler.
 Intel's and Motorola's microcontrollers have over hundred instructions.
Block diagram of PIC16F84 microcontroller:
Program memory (FLASH): Used for
storing a written program. It can be
programmed and cleared more than once,
it makes this microcontroller suitable for
device development.
EEPROM: Data memory that needs to
be saved when there is no supply. It is
usually used for storing important data
that must not be lost if power supply
suddenly stops.
RAM: Data memory used by a program during its execution. RAM are stored all
inter-results or temporary data during run-time.
PORTA and PORTB: Are physical connections between the microcontroller and
the
outside world. Port A has five, and port B has eight pins.
FREE-RUN TIMER: Is an 8-bit register inside a microcontroller that works
independently of the program. On every fourth clock of the oscillator it increments
its value until it reaches the maximum (255), and then it starts counting over again
from zero.
CENTRAL PROCESSING UNIT: It has a role of connective element between
other blocks in the microcontroller. It coordinates the work of other blocks and
executes the user program.

Internal Architecture of PIC16F84 microcontroller:

Memory organization:
PIC16F84 has two separate memory blocks, one for data and the other for
program. EEPROM memory with GPR and SFR registers in RAM memory make
up the data block, while FLASH memory makes up the program block.
Program memory: Program memory has been carried out in FLASH technology
which makes it possible to program a microcontroller many times before it's
installed into a device, and even after its installment if eventual changes in
program or process parameters should occur. The size of program memory is 1024
locations with 14 bits width where locations zero and four are reserved for reset
and interrupt vector.
Data memory: Data memory consists of EEPROM and RAM memories.
EEPROM memory consists of 64 eight bit locations whose contents is not lost
during loosing of power supply. EEPROM is not  directly addressable, but is
accessed indirectly through EEADR and EEDATA registers. As EEPROM
memory, there is a strict procedure for writing in EEPROM which must be
followed in order to avoid accidental writing.
 Locations of RAM memory are also called
GPR registers which can be accessed Data memory map
regardless of which bank is selected at the
moment. 
 First 12 locations in banks 0 and 1 are
registers of specialized function assigned with
certain blocks of the microcontroller. These
are called Special Function Registers.
Program memory map
Special purpose/function registers:
The special function registers can be classified into two sets, core
and peripheral.
Pin description:
PIC16F84 has a total of 18 pins. It is most frequently found in a DIP18 type.
Pin no.1: RA2 Second pin on port A. Has no additional function
Pin no.2 RA3 Third pin on port A. Has no additional function.
Pin no.3: RA4 Fourth pin on port A. TOCK1 which functions as a timer.
Pin no.4: MCLR Reset input and Vpp programming voltage of a
microcontroller
Pin no.5: Vss Ground of power supply.
Pin no.6: RBO Zero pin on port B. Interrupt input is an additional
function.
Pin no.7: RB1 First pin on port B. No additional function.
Pin no.8: RB2 Second pin on port B. No additional function.
Pin no.9: RB3 Third pin on port B. No additional function.
Pin no.10: RB4 Fourth pin on port B. No additional function.
Pin no.11: RBS Fifth pin on port B. No additional function.
Pin no.12: RB6 Sixth pin on port B. 'Clock' line in program mode.
Pin no.13: RB7 Seventh pin on port B. 'Data' line in program mode.
Pin no.14: Vdd Positive power supply pole.
Pin no.15: OSC2 Pin assigned for connecting with an oscillator
Pin no.16: OSC1 Pin assigned for connecting with an oscillator
Pin no.17: RA2 Second pin on port A. No additional function
Pin no.18: RA1 First pin on port A. No additional function.
I/O ports:
The PIC16F8X has two ports, PORTA and PORTB. Some port pins are
multiplexed with an alternate function for other features on the device.

PORTA and TRISA:

PORTA has 5 adjoining pins. The corresponding register for data direction is
TRISA at address 85h. Like with port B, setting a bit in TRISA register defines
also the corresponding port pin as input, and clearing a bit in TRISA register
defines the corresponding port pin as output.

PORTB and TRISB:

PORTB has adjoined 8 pins. The appropriate register for data direction is TRISB.
Setting a bit in TRISB register defines the corresponding port pin as input, and
resetting a bit in TRISB register defines the corresponding port pin as output.
THE
END
Instruction set of PIC16F84:
Programming, Simulation using MPLAB:
Microcontrollers with internal ADC and
DAC:
Some practical examples: