VLSI

VLSI
PHYSICAL DESIGN
PR E SEN TE D B Y –A R PI T YAD AV
Physical Design
• In integrated circuit design, physical design is a step in the standard
design cycle which follows after the circuit design. At this step, circuit
representations of the components (devices and interconnects) of the
design are converted into geometric representations of shapes which,
when manufactured in the corresponding layers of materials, will
ensure the required functioning of the components. This geometric
representation is called integrated circuit layout. This step is usually
split into several sub-steps, which include both design and verification
and validation of the layout.
VLSI Physical Design
VLSI physical designs process is lying between synthesis process and fabrication
process. The design come out from the physical design layer can be directly used to fabrication
process. Although physical design is organized as a single component, it consist of several
different and significant design steps. Physical design steps belong to back-end design stage
and it is totally depends on the results given by synthesis process. And also tech library support
is paramount important for the physical design stage to reserve area, power and lesser cross
talks. Clustering, floor planning, placing, routing, clock tree synthesis (CTS) are the major
ISAAC – Intelligent Systems and Advanced Computing
physical design steps. Following diagram illustrate the position of physical design in the
common ASIC design flow.
VLSI Physical Design
PHYSICAL DESIGN FLOW
Content
• DIVISION
• ASIC PHYSICAL DESIGN FLOW
• DESIGN NETLIST
• STEPS
DIVISION
• design is categorized into full custom and semi-custom design.
• Full-Custom: Designer has full flexibility on the layout design, no
predefined cells are used.
• Semi-Custom: Pre-designed library cells (preferably tested with DFM)
are used, designer has flexibility in placement of t
• he cells and routing
ASIC
An application-specific integrated circuit (ASIC)
is an integrated circuit (IC) chip customized for
a particular use, rather than intended for
general-purpose use. For example, a chip
designed to run in a digital voice recorder or a
high-efficiency bitcoin miner is an ASIC
ASIC PHYSICAL DESIGN FLOW
• The main steps in the ASIC physical design flow are:
• Design Netlist (after synthesis)
• Floorplanning
• Partitioning
• Placement
• Clock-tree Synthesis (CTS)
• Routing
• Physical Verification
• Layout Post Processing with Mask Data Generation
ASIC DESIGN FLOW
Design Netlist (after synthesis)
• Physical design is based on a netlist which is the end result of the Synthesis
process. Synthesis converts the RTL design usually coded in VHDL or Verilog
HDL to gate-level descriptions which the next set of tools can read/understand.
This netlist contains information on the cells used, their interconnections, area
used, and other details. Typical synthesis tools are:
• Cadence RTL Compiler/Build Gates/Physically Knowledgeable Synthesis (PKS)
• Synopsys Design Compiler
• During the synthesis process, constraints are applied to ensure that the design
meets the required functionality and speed (specifications). Only after the
netlist is verified for functionality and timing it is sent for the physical design
flow.
Floorplanning
• The second step in the physical design flow is floorplanning. Floorplanning is the process of
identifying structures that should be placed close together, and allocating space for them
in such a manner as to meet the sometimes conflicting goals of available space (cost of the
chip), required performance, and the desire to have everything close to everything else.
• Floor plan is the physical plan of the chip. In other way it is the initial phase of the physical
synthesis process. In the floor plan phase,
• o Physical plan of the chip
• o Size of the die
• o Boundaries and core area
• o Wire tracks o Pin locations
• o Positioning of blocks/macros on the die
Partitioning
• Partitioning is a process of dividing the chip into small blocks. This is
done mainly to separate different functional blocks and also to make
placement and routing easier. Partitioning can be done in the RTL
design phase when the design engineer partitions the entire design
into sub-blocks and then proceeds to design each module. These
modules are linked together in the main module called the TOP
LEVEL module. This kind of partitioning is commonly referred to as
Logical Partitioning. It was the first step of the physical design cycle...
Placement
• Before the start of placement optimization all Wire Load Models (WLM) are removed. Placement uses RC values from Virtual
Route (VR) to calculate timing. VR is the shortest Manhattan distance between two pins. VR RCs are more accurate than WLM
RCs.
• Placement is performed in four optimization phases:
• Pre-placement optimization
• In placement optimization
• Post Placement Optimization (PPO) before clock tree synthesis (CTS)
• PPO after CTS.
• Pre-placement Optimization optimizes the netlist before placement, HFNs (High Fanout Nets) are collapsed. It can also
downsize the cells.
• In-placement optimization re-optimizes the logic based on VR. This can perform cell sizing, cell moving, cell bypassing, net
splitting, gate duplication, buffer insertion, area recovery. Optimization performs iteration of setup fixing, incremental timing
and congestion driven placement.
• Post placement optimization before CTS performs netlist optimization with ideal clocks. It can fix setup, hold, max trans/cap
violations. It can do placement optimization based on global routing. It re does HFN synthesis.
• Post placement optimization after CTS optimizes timing with propagated clock. It tries to preserve clock skew.
Clock tree synthesis
• Clock is the caliber behind the sequential digital designs. Building a

clock throughout a complex design and synchronize the clock signal
is paramount important to have a good performance. Therefore
building the clock tree is important. Buffer insertion in clock path so
that all sequential elements receive the clock at the same time. This is
very crucial for faster timing closure
Clock tree synthesis
Fig –A ckt Fig –B Resp.

Routing
• In electronic design, wire routing, commonly called simply routing, is a step
in the design of printed circuit boards (PCBs) and integrated circuits (ICs). It
builds on a preceding step, called placement, which determines the location
of each active element of an IC or component on a PCB. After placement, the
routing step adds wires needed to properly connect the placed components
while obeying all design rules for the IC. Together, the placement and routing
steps of IC design are known as place and route.
• There are two types of routing in the physical design process, global routing
and detailed routing. Global routing allocates routing resources that are used
for connections. It also does track assignment for a particular net.
• Detailed routing does the actual connections. Different constraints that are to
be taken care during the routing are DRC, wire length, timing etc.
Physical verification
• Physical verification checks the correctness of the generated layout design.
This includes verifying that the layout
• Complies with all technology requirements – Design Rule Checking (DRC)

• Is consistent with the original netlist – Layout vs. Schematic (LVS)
• Has no antenna effects – Antenna Rule Checking
• This also includes density verification at the full chip level...Cleaning density
is a very critical step in the lower technology nodes
• Complies with all electrical requirements – Electrical Rule Checking (ERC)
Thank You
VLSI
Physical
Design

VLSI

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• Clock is the caliber behind the sequential digital designs. Building a

Fig –A ckt Fig –B Resp.

• Complies with all technology requirements – Design Rule Checking (DRC)

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