School of Engineering & Technology

Computer Science & Engineering Department

Subject - Computer Organization &Architecture ,

Sem-V

Digital Logic Design

Introduction
■ Brief introduction of the topic
■ Logic Gates
■ Introduction of logic circuits
■ Defining different types of logic circuits ,i.e, Combinational and Sequential
■ Defining different type of Combinational circuit ,i.e,
 Adders,Subtractors,Multipliers,Comparators,Multiplexers,Demultiplexers,
priority encoders, decoders.
■ Sequential circuit
■ Defining different type of Sequential circuit
 Flip-flops, Counters, Registers.
Definition
■ We study designing of digital circuits using logic gates in digital logic design. It is the basis
for digital computing and provides a fundamental understanding on how circuits and hardware
communicate within a computer.
■ A digital circuit is typically constructed from small electronic circuits called logic gates that can be
used to create combinational logic. Each logic gate is designed to perform a function of
Boolean logic when acting on logic signals.
Logic Gates
Logic Circuits

■ Logic circuits are combinational circuits that are constructed

from logic gates to create a combinational logic.
■ There are two types of logic circuits
1) Combinational Circuit
2) Sequential Circuit
Combinational
Circuit
Combinational Circuit
■ Combinational circuit is a type of digital circuit which is implemented by Boolean circuits, where
the output is a pure function of the present input only.
■ Different type of Combinational circuit are:
 Adders
 Subtractors
 Multipliers
 Comparators
 Multiplexers
 Demultiplexers
 Priority Encoders
 Decoders
K-Map
The Karnaugh map is a method of simplifying Boolean algebra expressions.
Adders
Half Adders
The addition of 2bits is called Half adder the input variables are augent and addent bits and output variables
are sum & carry bits. A and B are the two input bits.
Full Adder
Full Adder is the adder which adds three inputs and produces two outputs. The first two inputs are A
and B and the third input is an input carry as C-IN. The output carry is designated as C-OUT and the
normal output is designated as S which is SUM.
COUT = AB + C-IN (A EX – OR B)
Half Subtractor
Half subtractor is used to perform two binary digits subtraction.
Borrow = A
B = not-X AND Y = X.Y
Full Subtractor
A full subtractor is a combinational circuit that performs subtraction of two bits, one is minuend and
other is subtrahend, taking into account borrow of the previous adjacent lower minuend bit. The three
inputs A, B and Bin, denote the minuend, subtrahend, and previous borrow, respectively.
D= (A XOR B) XOR Bin
Bout = A’Bin + A’B + BBin
Multipliers
A multiplier is a combinational logic circuit that we use to multiply binary digits. 
Comparators
A magnitude digital Comparator is a combinational circuit that compares two digital or binary
numbers in order to find out whether one binary number is equal, less than or greater than the other
binary number. We logically design a circuit for which we will have two inputs one for A and other
for B and have three output terminals, one for A > B condition, one for A = B condition and one for
A < B condition.
1 Bit Comparator
A comparator used to compare two bits is called a single bit comparator. It consists of two inputs each for
two single bit numbers and three outputs to generate less than, equal to and greater than between two
binary numbers.

A>B: AB' A<B: A'B A=B: A'B' + AB

2 Bit Comparator
A comparator used to compare two binary numbers each of two bits is called a 2-bit Magnitude
comparator. It consists of four inputs and three outputs to generate less than, equal to and greater
than between two binary numbers.
From the above truth table K-map for each output can be drawn as follows:
From the above K-maps logical expressions for each output can be expressed as follows:
A>B:A1B1’ + A0B1’B0’ + A1A0B0’
A=B: A1’A0’B1’B0’ + A1’A0B1’B0 + A1A0B1B0 + A1A0’B1B0’
: A1’B1’ (A0’B0’ + A0B0) + A1B1 (A0B0 + A0’B0’)
: (A0B0 + A0’B0’) (A1B1 + A1’B1’)
: (A0 Ex-Nor B0) (A1 Ex-Nor B1)
A<B:A1’B1 + A0’B1B0 + A1’A0’B0
By using these Boolean expressions, we can implement a logic circuit for this comparator as given below:
Multiplexers
It is a combinational circuit which have many data inputs and single output depending on control or
select inputs.​For N input lines, log n (base2) selection lines, or we can say that for 2n input lines, n
selection lines are required. Multiplexers are also known as “Data n selector, parallel to serial
convertor, many to one circuit, universal logic circuit​”. Multiplexers are mainly used to increase
amount of the data that can be sent over the network within certain amount of time and bandwidth.
Now the implementation of 4:1 Multiplexer using truth table and gates
2​ : 1 MUX are required to
implement 4 : 1 MUX.
16 : 1 MUX using 4 : 1 MUX
Demultiplexer
A demultiplexer (or demux) is a device that takes a single input line and routes it to one of several digital
output lines. A demultiplexer of 2n outputs has n select lines, which are used to select which output line to
send the input. A demultiplexer is also called a data distributor.
1 : 4 demultiplexer
Boolean Expression
Y3 = (((D * S1) * S0))
Y2 = (((D * S1) * ~S0))
Y1 = (((D * ~S1) * S0))
Y0 = (((D * ~S1) *~S0))
Circuit diagram of 1:4 Demultiplexer
Encoders
An Encoder is a combinational circuit that performs the reverse operation of Decoder .It has
maximum of 2^n input lines and ‘n’ output lines, hence it encodes the information from 2^n
inputs into an n-bit code. It will produce a binary code equivalent to the input, which is active
High. Therefore, the encoder encodes 2^n input lines with ‘n’ bits.
Multiplexer
The 4 to 2 Encoder consists of four inputs Y3, Y2, Y1 & Y0 and two outputs A1 & A0. At any time,
only one of these 4 inputs can be ‘1’ in order to get the respective binary code at the output. The
figure below shows the logic symbol of 4 to 2 encoder :
Logical Expression for A1 and A0
A1 = Y3 + Y2 A0 = Y3 + Y1
Encoder
The 8 to 3 Encoder or octal to Binary encoder consists of 8 inputs : Y7 to Y0 and 3 outputs : A2,
A1 & A0. Each input line corresponds to each octal digit and three outputs generate corresponding
binary code.
Logical Expression for A2, A1 and A0
A2 = Y7 + Y6 + Y5 + Y4
A1 = Y7 + Y6 + Y3 + Y2
A0 = Y7 + Y5 + Y3 + Y1
Decimal to BCD Encoder –
The decimal to binary encoder usually consists of 10 input lines and 4 output lines. Each input line
corresponds to the each decimal digit and 4 outputs correspond to the BCD code. This encoder accepts the
decoded decimal data as an input and encodes it to the BCD output which is available on the output lines. 
Priority Encoder –
A 4 to 2 priority encoder has 4 inputs : Y3, Y2, Y1 & Y0 and 2 outputs : A1 & A0. Here, the input, Y3 has
the highest priority, whereas the input, Y0 has the lowest priority. In this case, even if more than one input is
‘1’ at the same time, the output will be the (binary) code corresponding to the input, which is having higher
priority.

Truth Table for Priority Encoders

The above two Boolean functions can be implemented as :
SEQUENCIAL
CIRCUIT
SEQUENCIAL CIRCUIT

■ As we know the combinational circuit does not use any memory. Hence the previous state of input
does not have any effect on the present state of the circuit. But in case of sequential circuit has
memory so output can vary based on input. This type of circuits uses previous input, output, clock and
a memory element.

■ So there are two types of input in the sequential circuit :

– External inputs which come from outside the circuit design and are not controlled by the circuit.
– Internal inputs which are a function of a previous output states.

■ The internal inputs and outputs are referred to as "secondaries". Secondary inputs are state variables
produced by the storage elements, where as secondary outputs are excitations for the storage elements.
SEQUENCIAL CIRCUIT
Key difference between sequential and
combinational circuit

1. In this output depends upon present as well as past input.

2. Speed is slow.
3. It is designed tough as compared to combinational circuits.
4. There exists a feedback path between input and output.
5. This is time dependent.
6. Elementary building blocks: Flip-flops
7. Mainly used for storing data.
8. Sequential circuits have capability to store any state or to retain earlier state.
9. As sequential circuits are clock dependent they need triggering.
10. These circuits have memory element.
11. It is not easy to use and handle as compare to combinational circuit.
 Two Main Types of Sequential Circuits
■ There are mainly two types of sequential circuit, synchronous and asynchronous.

1. Synchronous
■ In synchronous sequential circuits, the state of device changes at discrete times in response to a
clock signal.
■ In synchronous circuits, the inputs are pulses with certain restrictions on pulse width and
propagation delay. Thus synchronous circuits can be divided into clocked and un-clocked or
pulsed sequential circuits.

2. Asynchronous 
■ In asynchronous circuits, the state of the device changes in response to changing inputs.
■ An asynchronous circuit does not have a clock signal to synchronize its internal changes of the
state. Hence the state change occurs in direct response to changes that occur in primary input
lines. An asynchronous circuit does not require the precise timing control from flip-flops
Synchronous
Clocked Sequential Circuit
The clocked sequential circuits have flip-flops or gated latches for its memory
elements. There is a periodic clock connected to the clock inputs of all the
memory elements of the circuit to synchronize all the internal changes of state.
Hence the operation of the circuit is controlled and synchronized by the periodic
pulse of the clock.

Unclocked Sequential Circuit

In an unclocked sequential circuit requires two consecutive transitions between 0 and 1 to alternate the state
of the circuit. An unclocked mode circuit is designed to respond to pulses of certain durations which do not
affect the circuit’s behaviour.
The synchronous logic circuit is very simple. The logic gates which perform the operations on the data,
require a finite amount of time to respond to the changes in the input.
Asynchronous
Asynchronous logic is more difficult to design and it has some
problems compared to synchronous logic. The main problem
is that the digital memory is sensitive to the order that their
input signals arrive them, like, if two signals arrive at a flip-
flop at the same time, which state the circuit goes into can
depend on which signal gets to the logic gate first.

Asynchronous circuits are used in critical parts of synchronous

systems where the speed of the system is a priority, like as
in microprocessors and digital signal processing circuits.

Types of asynchronous sequential circuit:

• Flip-flop
• Register
• Counter
 Flip-flop
■ A flip flop is an electronic circuit with two stable states that can be used to store binary data.
■ The stored data can be changed by applying varying inputs.
■ Flip-flops and latches are fundamental building blocks of digital electronics systems used in computers,
communications, and many other types of systems.
■ Flip-flops and latches are used as data storage elements. It is the basic storage element in sequential logic.
■ The basic difference between a latch and a flip-flop is a gating or clocking mechanism.

■ Types of flipflop:

 SR Flip-flop
 JK Flip-flop
 R Flip-flop
 T Flip-flop
 SR Flip-flop
■ There are majorly 4 types of flip flops, with the most common one being SR flip flop.
■ This simple flip flop circuit has a set input (S) and a reset input (R).
■ In this circuit diagram, the output is changed (i.e. the stored data is changed) only when you give an
active clock signal. Otherwise, even if the S or R is active the data will not change.
■ So by putting the clock in inactive state or zero state we can generate high impedance state in which the
input does not effect the output state Characteristic Table
Present Inputs Present State Next State
0
Q(t+1)=0 S R Qt Qt+1
(0+1)’ =0
0 0 0 0
0 0 1 1
0 1 0 0
0 1 1 0
1 0 0 1
(0+0)’ =1
1 0 1 1
0
1 1 0 x
1 1 1 x
The maximum possible groupings
of adjacent ones are shown in the
figure. Therefore, the simplified
expression for next state Q t+1 is
 State Table Excitation table
S R Qt+1 States Inputs
Presen
Next S R
t
0 0 Qt
0 0 0 X
0 1 0
0 1 1 0
1 0 1
1 0 0 1
1 1 - 1 1 X 0

=> Q(t+1)=S+R′Q(t)
 An excitation table shows the minimum inputs that are
necessary to generate a particular next state (in other
words, to "excite" it to the next state) when the current
state is known.
JK Flip-flop
■ JK flip-flop is the modified version of SR flip-flop. It operates with only positive clock transitions or
negative clock transitions

■ This circuit has two inputs J & K and two outputs Q t & Q t’. The operation of JK flip-flop is similar to
SR flip-flop. Here, we considered the inputs of SR flip-flop as S = J Qt’ and R = K Qt  in order to
utilize the modified SR flip-flop for 4 combinations of inputs.

■ Here, Qt & Q t+1 are present state & next state respectively. So, JK flip-flop can be used for one of
these four functions such as Hold, Reset, Set & Complement of present state based on the input
conditions, when positive transition of clock signal is applied.

■ As JK flipflop is advance form of SR flip flop which mainly design to overcome the limitation of S R
circuit that is in case of SR flipflop when S and R both input become one then the output become invalid
that is both Qt and Qt’ output getting the same value.

■ So in this case the output produce by the nor gate is fed as input in nand gate.
 The following table shows the characteristic
table of JK flip-flop.
The circuit diagram of JK flip-flop is shown
in the following figure. Present Inputs Present Next State
State
0 J K Qt Qt+1
0
0 0.0 0 0 0 0 0
(1+0’)
0 0 1 1
0 1 0 0
1 0 1 1 0
0 (0+0)’
0 0.1 1 0 0 1
1 1 0 1 1
1 1 0 1
1 1 1 0
 By using three variable K-Map, we can get the  State table 
simplified expression for next state, Qt+1. Three
variable K-Map for next state, Qt+1 is shown in J K Qt+1
the following figure. 0 0 Qt
0 1 0
1 0 1
1 1 Qt'

 Excitation table

States Inputs
The maximum possible groupings of adjacent ones
are already shown in the figure. Therefore, Present Next J K
the simplified expression for next state Qt+1 is 0 0 0 X
0 1 1 X
Q(t+1)=JQ(t)′+K′Q(t)
1 0 X 1
1 1 X 0
 T Flip flop
■ If we do some modification in input values of JK flipflop then we can obtain this flipflop.
■ T flip-flop is the simplified version of JK flip-flop. It is obtained by connecting the same input ‘T’ to both
inputs of JK flip-flop.

■ Or we can say if we use JK flipflop in limited pattern then it work like T flipflop.
■  It operates with only positive clock transitions or negative clock transitions.

■ This circuit has single input T and two outputs Qt & Qt’. 
■ The operation of T flip-flop is same as that of JK flip-flop. Here, we considered the inputs of JK flip-flop
as J = T and K = T in order to utilize the modified JK flip-flop for 2 combinations of inputs. So, we
eliminated the other two combinations of J & K, for which those two values are complement to each other
in T flip-flop.

■ Here, Qt & Qt+1 are present state & next state respectively. So, T flip-flop can be used for one of these
two functions such as Hold, & Complement of present state based on the input conditions, when positive
transition of clock signal is applied.
The circuit diagram of T flip-flop is shown in the
following figure. The following table shows
the characteristic table of T flip-flop.

Inputs Present Next State

State

T Qtt Qt+1

0 0 0

0 1 1

1 0 1

1 1 0
 State table

T Qt+1
K-Map for T flip
flop 0 Qt
T’ T
1 Qt’
Qt’ 1
Qt 1
Excitation tables
Q(t+1)=T′Q(t)+TQ(t)′Q(t+1)
States Input
=T′Q(t)+TQ(t)′
Present Next T
⇒Q(t+1)=T⊕Q(t) 0 0 0
0 1 1
1 0 1
Or from the above characteristic
table, we can directly write the next 1 1 0
state equation
The output of T flip-flop always toggles for every
positive transition of the clock signal, when input
T remains at logic High 11. Hence, T flip-flop can
be used in counters.
 D flipflop
■ D flip-flop operates with only positive clock transitions or negative clock transitions. 
■ Whereas, D latch operates with enable signal. That means, the output of D flip-flop is insensitive to the
changes in the input, D except for active transition of the clock signal.
■ This circuit has single input D and two outputs Qt & Qt’.
■ D flipflop is just like a T flipflop but the only difference is that while inserting the inputs one input in
‘and’ gate is complimented by using not gate in D flip-flop.

Inputs Present Next State

State
D Qt Qt+1
0 0 0
0 1 0
1 0 1
1 1 1
Therefore, D flip-flop always Hold the information, which is available on data input, D of earlier positive
transition of clock signal. From the above state table, we can directly write the next state equation as :
Qt+1 = D State table 

K-Map for T flip flop D Qt+1

0 0
1 1

Excitation table

States Input
Qt+1 = D
Present Next D
0 0 0
0 1 1
Next state of D flip-flop is always equal to data input, D
for every positive transition of the clock signal. Hence, D 1 0 0
flip-flops can be used in registers, shift registers and 1 1 1
some of the counters.
Register
Registers are logic units used for storing strings of bits in a sequential logic circuit. Registers are generally
constructed using D flip-flops
The simplest register is a 1-bit register. A 1-bit register is simply a single D flip-flop. It holds a logical value of
exactly one bit in length. Larger registers can hold longer strings of bits. For example, an 8-bit register holds an
8-bit logical value (i.e. 10110110), and it is formed by a collection of eight D flip-flops. In order to form a
register form a collection of flip-flops, the flip-flops must all run on the same clock signal.
In general, there are two major types of registers: Parallel-Load Registers and Shift Registers.
Parallel-Load Registers
Parallel-load registers are a type of register where the individual bit values in the register are loaded
simultaneously. More specifically, every flip-flop within the register takes an external data input, and these
inputs are loaded into the flip-flops on the same edge in a clock cycle.
Pictured above is a simple 4-bit parallel-load register where D0, D1, D2, and D3 are the individual data
bits; Q0, Q1, Q2, and Q3 form the output value (as a 4-bit word Q3Q2Q1Q0); and Clk is the single clock
signal.
Shift Registers
The Shift Register is another type of sequential logic circuit that can be used for the storage or the transfer
of binary data
This sequential device loads the data present on its inputs and then moves or “shifts” it to its output once
every clock cycle, hence the name Shift Register.
Shift registers are formed by flip-flops that have been linked to each other in various ways - allowing one
flip-flop to assume the current value of another flip-flop within the register (also known as shifting).
Shift register IC’s are generally provided with a clear or reset connection so that they can be “SET” or
“RESET” as required. Generally, shift registers operate in one of four different modes with the basic
movement of data through a shift register being:

• Serial-in to Parallel-out (SIPO)  -  the register is loaded with serial data, one bit at a time, with the
stored data being available at the output in parallel form.

• Serial-in to Serial-out (SISO)  -  the data is shifted serially “IN” and “OUT” of the register, one bit at a
time in either a left or right direction under clock control.

• Parallel-in to Serial-out (PISO)  -  the parallel data is loaded into the register simultaneously and is
shifted out of the register serially one bit at a time under clock control.

• Parallel-in to Parallel-out (PIPO)  -  the parallel data is loaded simultaneously into the register, and
transferred together to their respective outputs by the same clock pulse.
Counter
 A Counter is a device which stores (and sometimes displays) the number of times a particular event or process
has occurred, often in relationship to a clock signal.
Counters are used in digital electronics for counting purpose, they can count specific event happening in the
circuit. For example, in UP counter a counter increases count for every rising edge of clock. Not only
counting, a counter can follow the certain sequence based on our design like any random sequence
0,1,3,2… .They can also  be designed with the help of flip flops.

Counter Classification
Counters are broadly divided into two categories
1. Asynchronous counter
2. Synchronous counter
 Asynchronous Counter
In asynchronous counter we don’t use universal clock, only first flip flop is driven by main clock and the
clock input of rest of the following flip flop is driven by output of previous flip flops. We can understand it
by following diagram-

It is evident from timing

diagram that Q0 is changing
as soon as the rising edge of
clock pulse is encountered,
Q1 is changing when rising
edge of Q0 is
encountered(because Q0 is
like clock pulse for second
flip flop) and so on. In this
way ripples are generated
through Q0,Q1,Q2,Q3 hence
it is also
called RIPPLE counter.
Synchronous Counter
Unlike the asynchronous counter, synchronous counter has one global clock which drives each flip flop so
output changes in parallel. The one advantage of synchronous counter over asynchronous counter is, it can
operate on higher frequency than asynchronous counter as it does not have cumulative delay because of
same clock is given to each flip flop.

From circuit diagram we

see that Q0 bit gives
response to each falling
edge of clock while Q1 is
dependent on Q0, Q2 is
dependent on Q1 and
Q0 , Q3 is dependent on
Q2,Q1 and Q0.
Reference
 Computer Organization and Architecture 9th edition by William Stallings.

 https://en.wikipedia.org/wiki/Excitation_table#:~:text=In%20order%20to%20obtain%20the,t%20%2B%
201)%20as%20desired
.

 https://practice.geeksforgeeks.org/courses/dsa-self-paced?gclid=CjwKCAjww5r8BRB6EiwArcckCxXqXbK
-bJFQ_tDSKLiCi-xR12FlKlsvQ-lnFy7S8lIrvIj_b3ToRxoCW8gQAvD_BwE

 https://www.tutorialspoint.com/computer_logical_organization/sequential_circuits.htm
THANK
YOU