Chapter 4

Designing combinational logic

circuit
 4.1 NMOS and PMOS transistor

 A FET (Field Effect Transistor) is a voltage controlled device where its current carrying
ability is changed by applying an electronic field.
 A commonly used type of FET is the Metal Oxide Semiconductor FET (MOSFET). MOSFET
are widely used in integrated circuits and high speed switching applications.
 MOSFET work by inducing a conducting channel between two contacts called the source
and the drain by applying a voltage on the oxide-insulated gate electrode.
 There are two main types of MOSFET called nMOSFET (commonly known as NMOS) and
pMOSFET (commonly known as PMOS) depending on the type of carriers flowing through
the channel.
 4.1 NMOS & PMOS TRANSISTOR

NMOS PMOS

Built with n-type source and drain Built with p-type source and drain

P-type substrate N-type substrate

Majority carriers are electrons Majority carriers are holes

Cross section Cross section

4.2 STATIC CMOS INVERTER
4.2.1 NMOS FUNCTION AS SWITCH
4.2.1 PMOS FUNCTION AS SWITCH
4.2.2 Cmos inverter PUN & PDN

• CMOS inverter consists

of NMOS & PMOS
transistor connected in
series:
– PMOS transistor
functions as a pull-
up network
– NMOS transistor
functions as a pull-
down network
 4.2.2 Cmos inverter PUN & PDN

 Pull-up network- a network that provides a low

resistance path to Vdd when output is logic '1' and
provides a high resistance to Vdd otherwise.
 Pull-down network - a network that provides a
low resistance path to Gnd when output is logic '0'
and provides a high resistance to Gnd otherwise.
4.2.2 FUNCTION OF CMOS INVERTER

 An inverter circuit outputs voltage representing the opposite

logic-level to its input.
 Its main function is to invert the input signal applied.
 If the applied input is low then the output becomes high and
vice versa.
 Inverters can be constructed using a single NMOS transistor or a
single PMOS transistor coupled with a resistor.
4.2.2 CMOS INVERTER

SYMBOL
4.2.2 CMOS INVERTER OPERATION

INPUT A = LOGIC ‘1’ INPUT A = LOGIC ‘0’

1. NMOS is ON, PMOS is OFF. 1. PMOS is ON, NMOS is OFF.

2. NMOS will transfer logic ‘0’ (GND) to 2. PMOS will transfer logic ‘1’
the output. (VDD) to the output.
3. Output Y = Logic ‘0’ 3. Output Y = Logic ‘1’

TRUTH TABLE
4.3 STATIC CMOS LOGIC CIRCUITS

 The complementary CMOS circuit style falls under a broad class of logic circuits called static
circuits in which at every point in time (except during the switching transients),each gate
output is connected to either VDD or Vss via a low-resistance path.
 Also,the outputs of the gates assume at all times the value of the Boolean function
implemented by the circuit (ignoring, once again, the transient effects during switching
periods).
 This is in contrast to the dynamic circuit class, which relies on temporary storage of signal
values on the capacitance of high-impedance circuit nodes.
Combinational Logic Sequential Logic Circuit
Circuit (Non- (Regenerative)
regenerative)
 This is accomplished by connecting one or
 Circuits that have the property that more outputs intentionally back to some
at any point in time, the output of inputs.
the circuit is related to its current  Consequently, the circuit “remembers” past
input signals by some Boolean events and has a sense of history.
expression  A sequential circuit includes a
 No intentional connection between combinational logic portion and a module
outputs and inputs is present. that holds the state.
 Output = f(In)  Example circuits are registers, counters,
oscillators and memory.
 Output = f(In, previous In)
 4.4 STATIC CMOS
4.4.1 Block Diagram PUN & PDN
VDD

In1
In2 PUN PMOS Only
In3

F=G

In1
In2 PDN NMOS Only
In3

VSS

PUN and PDN are Dual Networks

Static CMOS Logic Circuit
 Example schematic diagram
for CMOS inverter consist of
NMOS & PMOS transistor
connect in series :
 PMOS transistor function as Pull-up
a pull-up network (PUN) Network

 NMOS transistor functions Input Output

as a pull-down network Pull-down

(PDN) Network
NMOS Transistors in Series/Parallel
Connection
o Transistors can be thought as a switch controlled by its gate signal.
o NMOS switch closes when switch control input is high

A B

X Y Y = X if A and B

X B Y = X if A OR B
Y
PMOS Transistors in Series/Parallel
Connection
PMOS switch closes when switch control input is low

A B

X Y Y = X if A AND B = A + B

X B Y = X if A OR B = AB
Y
4.2.2 AND or NAND Function Formed In PUN & PDN

 Identify the AND and NAND logic gate.

AND gate NAND gate

A
F
B

F= A.B
F=A.B
AND or NAND Function Formed In PUN &
PDN

Pull - Up Network Pull - Down Network

4.2.3 OR or NOR Function Formed In PUN & PDN

 Identify the OR and NOR logic gate.

OR gate NOR gate

F= A+B F= A+B
OR or NOR Function Formed In PUN &
PDN

Pull - Up Network Pull - Down Network

4.3 STATIC CMOS LOGIC CIRCUIT

General structure for all CMOS configuration:

VDD

PMOS Network
f
Input Output

NMOS Network
f
4.3.1 Static CMOS Logic Circuit

Step to construct :
1. Identify the function f to determine PMOS
network.

2. Identify the function f to determine NMOS

network.

3. AND function is obtained when the

transistor are in series, and OR function is
obtained when the transistors are in parallel.
 4.3.1 Static CMOS Logic Circuit
How to construct a CMOS logic circuit for 2 input NAND gate?

2. Solve the Boolean equation for PMOS

A and NMOS.
F
B
(a)F = A + B (PMOS Network)
(b)F = A . B (NMOS Network)
1. Produce the Boolean
equation from the logic 3. PMOS are connected in parallel because F
gate. is an OR function.

F=A.B 4. NMOS are connected in series because F is

an AND function.
 Static CMOS Logic Circuit
2 input NAND gate 3 input NAND gate
Static CMOS Logic Circuit
4 input NAND gate CMOS logic circuit
 Static CMOS Logic Circuit

How to construct a CMOS logic circuit for 2 input NOR gate?

2. Solve the Boolean equation for PMOS

and NMOS.

(a)F = A . B (PMOS Network)

(b)F = A + B (NMOS Network)
1. Produce the Boolean
equation from the logic gate. 3. PMOS are connected in series because F is
an AND function.
F=A+B
4. NMOS are connected in parallel because F
is an OR function.
 Static CMOS Logic Circuit

2 input NOR gate 3 input NOR gate

Static CMOS Logic Circuit
4 input NOR gate
 Static CMOS Logic Circuit

How to construct a CMOS logic circuit for Exclusive OR function?

2. Solve the Boolean equation for PMOS

and NMOS.

(a)C = A . B + A . B (PMOS Network)

1. Produce the Boolean (b)C =(A +B ) . (A +B) (NMOS

equation from the logic gate. Network)
3. Construct the schematic diagram based on
C=A.B+A.B their operation.

C=A B
Static CMOS Logic Circuit- 2 input X-OR gate
2-input X-NOR gate
4.3.2 Transistor Sizing

Transistor Sizing

Not all gates need to have the

same delay.

Not all inputs to a gate need to

have the same delay.

Adjust transistor sizes to achieve

desired delay.
 Transistor Sizing

 Transistor sizing
◦as long as fan-out capacitance dominates

 Progressive sizing:
When designing static CMOS circuits, balance the driving
strengths of the transistors by making the PMOS section wider
than the NMOS section to :

◦maximize the noise margins and

◦obtain symmetrical characteristics
2-input NAND Gate Sizing

 What will be the optimum size of the transistors

which can optimize the circuit in terms of
power, delay and area?
 The Aspect Ratio of an inverter is made to be
Wp/Wn =μr (the mobility ratio) so that the pull
up and the pull down have the same drive
strength, ie the same resistance.
 The aim is to equalize rise and fall time,
assuming that minimum width of an inverter is
Wnmin, for tr = tf , let Lp= Ln= Lmin. That is, if
=3, then Wp = 3Wn. Then, the sizing of Wn and
Wp is shown in the figure. r np WW   r 
2-input NOR Gate Sizing
 Since the PMOS transistors are in
series, the resistance adds up. As
such, we need to
 multiply the width in order to
reduce resistance. That is, for
Wn=Wn min in this circuit,
 Wp=6Wmin, where 6 = 2x3, 2 for
resistance and 3 for r  .
4.4 Design Combinational Logic For Complex
Boolean Function

For example : Given below is a Boolean

equation with four input.

f = A ( B + CD )
 Static CMOS Logic Circuit

How to construct a CMOS logic circuit with 4 input?

1. Solve the Boolean equation for PMOS and NMOS.

2. f = A + (B  (C + D) ) (PMOS Network)
3. f = A ( B + CD) (NMOS Network)
4. PMOS: C and D are connected in parallel, then this
connection is in series with B. The network is then connected
in parallel with A.
5. NMOS: C and D are connected in series, then this
connection is in parallel with B. The network is then connected
in series with A.
 Static CMOS Logic Circuit

Construct the Pull-UP & Pull-Down Network:

Pull - Up Pull - Down

VDD
f = A (B + CD)
A
A B

C
C D B
D

f = A + (B . (C+D))
 Static CMOS Logic Circuit

Combine the Pull-up Network and the Pull-down

Network to form the logic circuit.
VDD

A B

C D

f
A

C
B
D
 Static CMOS Logic Circuit

Other examples:

Try to construct CMOS logic circuit and stick

diagram for the following functions:

1. f = x + yz

2. f = AB + BC

3. f = A + (BC + D)
 4.12 DYNAMIC CMOS LOGIC

 The logic circuits we have studied so far are of the static

type. That is, every node has a low resistance path to VDD or
ground (the voltage of each node is well defined at all times).
No node is left floating.

 Dynamic logic circuits rely on the storage of signal voltages

on parasitic capacitance at certain nodes. It needs to be
periodically refreshed; thus the clock with specified minimum
frequency is essential.
4.12.1 Basic Construction of Dynamic CMOS Logic
 4.12.1 Two Major Phases in Dynamic Logic
Precharge
 CLK = 0, Out is precharged to VDD by Mp.
 Me is turned off, no dc current flows
 (regardless of input values)

Evaluation
 CLK = 1, Me is turned on, Mp is turned off.
 Output is pulled down to zero depending
 on the values on the inputs. If not,
 precharged value remains on CL.
 Important: Once Out is discharged, it cannot be charged again!
Gate input can make only one transition during evaluation
4.12.2 Advantages of Dynamic Logic
 4.14 Design Dynamic CMOS Logic

Task :
1. Construct 2 input dynamic Nand gate.
2. Construct a dynamic CMOS logic circuit for this Boolean equation
F = AB + BC
3. Design a four input dynamic nand gate.