FIELD EFFECT TRANSISTORS (FET)

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 INTRODUCTION

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• Current-controlled and voltage-controlled amplifiers

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CONSTRUCTION

•
A JFET is a three terminal semiconductor device with one terminal capable of controlling the current between the other two terminals. Major part of the
structure consists of an n or p type channel of semiconductor material having two metal contacts at its ends called the Drain (D) and the Source (S). A third
contact, the gate (G) is connected to a p or n – type region between the Drain and the Source which forms a p –n junction. In absence of an applied potential
the two p-n junctions under no bias conditions, result in a depletion region at each junction – resembling the same region of a diode under no bias conditions.

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N – Channel JFET
VGS = 0 V, VDS Some Positive Value
IG = 0 A

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 PINCH-OFF and SATURATION LEVEL

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 Characteristics when VGS < 0 V

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 OPERATION

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 P – Channel JFET

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 Symbols
N – Channel and P - Channel
•

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 TRANSFER CHARACTERISTIC

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 Applying Shockley’s Equation

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 Summary Shockley’s Equation

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 OPERATING REGION

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 IMPORTANT RELATIONSHIPS

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 BIASING

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 JFET Fixed Bias
𝑉 𝐷𝐷 =𝑉 𝐷𝑆 + 𝐼 𝐷 𝑅 𝐷

𝑽 𝑫𝑺 =𝑽 𝑫𝑫 − 𝑰 𝑫 𝑹 𝑫
VGG + IGRG + VGS = 0
Since IG = 0 𝑽 𝑫 =𝑽 𝑫𝑫 − 𝑰 𝑫 𝑹 𝑫
VGS = - VGG

RG is present to limit
current in case VGG is
connected with wrong
polarity
This would forward bias
the gate-source junction
causing high currents,
which would destroy the
transistor
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 DC Analysis for JFET Fixed Bias Network

VGS = - VGG

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 JFET Fixed Bias Plotting Shockley’s Equation

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 JFET Fixed Bias Graphical Solution

𝑽 𝑮𝑺 =−𝑽 𝑮𝑮

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 JFET Fixed Bias

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 Graphical Solution for JFET Fixed Bias

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 Output equations and Load line

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 SELF BIAS CONFIGURATION

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 JFET Self Bias Configuration
𝐼 𝐺=0
𝑉 𝐷𝐷 = 𝐼 𝐷 𝑅 𝐷 +𝑉 𝐷𝑆 + 𝐼 𝐷 𝑅𝑆
𝑉 𝐺=0
𝑽 𝑫𝑺 =𝑽 𝑫𝑫 − 𝑰 𝑫 ( 𝑹 𝑫 + 𝑹 𝑺 )
𝑉 𝐺=𝑉 𝐺𝑆 + 𝐼 𝐷 𝑅𝑆=0

𝑽 𝑮𝑺 =− 𝑰 𝑫 𝑹𝑺

𝑽 𝑫 =𝑽 𝑫𝑫 − 𝑰 𝑫 𝑹 𝑫

𝑽 𝑺= 𝑰 𝑫 𝑹 𝑺

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 JFET Self Bias Transconductance Curve

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 JFET Self Bias Load Line

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 JFET Self Bias

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 JFET Self Bias Transconductance Curve

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 Graphical Solution of JFET Self Bias

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 JFET Self Bias Effect on Variation of RS

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 Self Bias
Self drill question

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 JFET Voltage Divider Bias
𝑅 2(𝑉 𝐷𝐷 )
𝑉 𝐺=
𝑅1 + 𝑅2
𝑽 𝑫𝑺 =𝑽 𝑫𝑫 − 𝑰 𝑫 ( 𝑹 𝑫 + 𝑹 𝑺 )
𝑉 𝐺=𝑉 𝐺𝑆 + 𝐼 𝐷 𝑅𝑆

𝑽 𝑮𝑺 =𝑽 𝑮 − 𝑰 𝑫 𝑹𝑺

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 JFET Voltage Divider Bias Load Line

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 The Effect of RS on Q-point

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 JFET Voltage Divider Bias

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 JFET Voltage Divider Bias Q-point

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 Voltage Divider Bias
Self drill question

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 BREAK

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 MOSFETs

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 MOSFETs

MOSFETs have characteristics similar to JFETs and

There are 2 types of MOSFET’s:

• Depletion type MOSFET (D-MOSFET)

• Operates in Depletion mode the same way as a JFET when VGS  0

• Enhancement type MOSFET (E-MOSFET)

• Operates in Enhancement mode

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 MOSFET Handling

MOSFETs are very static sensitive. Because of the very

Protection:
• Always transport in a static sensitive bag
• Always wear a static strap when handling MOSFETS
• Apply voltage limiting devices between the Gate and
Source, such as back-to- back Zeners to limit any
transient voltage

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 D-MOSFET Symbols

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 Specification Sheet

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 Depletion Mode MOSFET Construction

The Drain (D) and Source (S) leads connect to the to n-doped regions
These N-doped regions are connected via an n-channel
This n-channel is connected to the Gate (G) via a thin insulating layer of SiO 2
The n-doped material lies on a p-doped substrate that may have an additional
terminal connection called SS

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 Basic Operation
A D-MOSFET may be biased to operate in two modes:
the Depletion mode or the Enhancement mode

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 p-Channel Depletion Mode MOSFET

The p-channel Depletion mode MOSFET is similar to the n-channel

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 D – MOSFETs biasing

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 D-MOSFET Self Bias

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Determining the Q-point for D-MOSFET Self Bias

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 N Channel D-MOSFET Voltage Divider Bias

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 Q Point of D-MOSFET Voltage Divider Bias

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Effect on Change in Q Point with Variation of RS

With an N Channel
D-MOSFET,
VGS may be positive

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 D-MOSFET Fixed Bias

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 Enhancement Type MOSFETs
E - MOSFETs

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 Enhancement Mode MOSFET Construction

The Drain (D) and Source (S) connect to the to n-doped regions
These n-doped regions are not connected via an n-channel without an external
voltage
The Gate (G) connects to the p-doped substrate via a thin insulating layer of
SiO2
The n-doped material lies on a p-doped substrate that may have an additional
terminal connection called SS
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 Specification Sheet

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 E-MOSFET Symbols

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 Basic Operation
The Enhancement mode MOSFET only operates in the enhancement mode.

VGS is always positive

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 Transfer Curve

ID(on)
2 k=
To determine ID given VGS: ID = k (VGS - VT) (VGS(ON) - VT)2
where VT = threshold voltage or voltage at which the MOSFET
turns on.
k = constant found in the specification sheet
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 p-Channel Enhancement Mode MOSFETs
The p-channel Enhancement mode MOSFET is similar to the n-
channel except that the voltage polarities and current
directions are reversed.

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 E-MOSFET BIASING

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 E-MOSFET Feedback Bias

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DC Equivalent For the E-MOSFET Feedback Bias

IG = 0

VGS = VDS

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Transfer Curve for the E-MOSFET Feedback Bias

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Determining the Q-point for E-MOSFET Feedback Bias

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 Q-point for the E-MOSFET Fixed Bias

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 EMOS Feedback Bias Example

VGSTH = 4V
VGSon = 7.5V
IDon = 5mA
VDD = 22V

IDon
k=
(VGSon - VGSTH)2
ID = k(VGS - VGSTH)2

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 EMOS Feedback Example

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 Voltage Divider Bias for an N E-MOSFET

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 Q-point for E-MOSFET Voltage Divider Bias

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 Summary Table

JFET D-MOSFET E-MOSFET

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