Snubber Circuits
Snubber Circuits
Snubber Circuits
Snubber Circuits
Outline
B. Diode Snubbers
C. Turn-off Snubbers
D. Overvoltage Snubbers
E. Turn-on Snubbers
F. Thyristor Snubbers
di V
Df d
=
d t Lσ
+ Lσ Io
Rs
Io i (t) t
Df
Vd Df Cs I rr
Sw
-
v (t) t
Df Vd
• Lσ = stray inductance
d iLσ
• Diode br ea kd o wn i f V d + L σ > BV BD
dt
Lσ
• Simplified snubber -
the capacitive snubber
+ Rs
Lσ
Vd Diode cathode
snap-off anode
- +
+
Vd v Cs
Cs
-
i Df -
t
• R s= 0
• Worst case assumption-
diode snaps off instantaneously •v = -v
Cs Df
at end of diode recovery
d 2 v Cs v Cs Vd
• Gove rning e qua t ion - + =
dt 2 LσCs LσCs
⎡ I ⎤2
1 ⎢ rr⎥
• ωo = ; C base = L σ ⎢ ⎥
LσCs ⎣V d ⎦
⎧ Cbase ⎫
• V cs,m ax = V d
⎨1 + 1 +
⎬
⎩ Cs ⎭
3
V
Cs,max
V
d
C
base
C
s
Lσ i(t)
d2 i di i
+ - • Gove rning eq ua t ion L σ + Rs + = 0
2 d t C
Rs dt s
Vdf e-αt
Vd (t) = - 1 - η cos(φ)
sin(ωat -φ + ζ) ; R s ≤2 R b
Rs ⎡ ⎤
2 1 -1 ⎢ (2-x) η ⎥
ωa = ωo 1- (α/ ωo) ; α = 2 L ; ωo = ; φ = tan ⎢ ⎥
σ LσCs ⎣ 4 - ηx2⎦
Cs Rs Vd Lσ [Irr]2
η = C ; x = R ; Rb = I ; Cb = 2 ; ζ = tan-1(α/ωa)
b b rr Vd
• At t = t m v Df (t ) = V m a x
R
s,opt
C =C
s base = 1.3
t a n -1 ( ωa/ α)
R
φ - ξ base
• tm = ωa + ω ≥0
a 2
V m ax V
η-1 - x
max
• = 1 + 1 + e xp(-αtm )
Vd V
d
Cs Rs 1
• η = and x=
Cbase R base
RI
s rr
Ls I rr2 Vd V
V d2 Irr 0
0 1 R 2
s
R
base
L I /2
3 s rr
W
R
L I /2
s rr
V
0 max
for R = R
s s,opt
0 V
d
0
0
0
0
0
0
0
0
0
0
0 0
0 0 0 0 0
0 0
0
1
R
s,op
R
base
2 3
0 1
C /C
s base
to t t t t
t 3 4 5 6
1
• L1 , L , L = stray inductances
2 3
Switching trajectory of switch
• Lσ = L1 + L 2 + L 3 idealized
i sw switching
t6 t 5 loci
t turn-off
o • Overvoltage at turn-off
t due to stray inductance
1
turn-on
• Overcurrent at turn-on due to
diode reverse recovery
t
4 t3 vsw
Vd
Turn-off
D snubber
i I
f
+ o
D
F
R
S
s
w
i
-
C
C
s
s
• Simplifying assumptions
f
V 1. No stray inductance.
d
I -i
o
sw
C
s
sw sw
sw
I
o
i
i
i
D
f D
D
f
f
t
t
t
fi fi
fi
C
s
V
d
C
s
C = C C > C
C < C s
s s1 s
s1 s
v
sw
t
rr
I I
D o o
f
• Ds shorts out Rs
R i I
s
during Sw turn-off. D
f
rr
• During Sw turn-on,
V
d
I
S D o
Ds reverse-biased and
w s i R
sw s
C
s
Cs discharges thru Rs.
I
rr
discharge
• Turn-on with Rs > 0
t
rr
of C
• Turn-on with Rs = 0
v
in Rs rather than in Sw.
sw
d
I
o
in Sw. • Voltage fall time kept quite
short.
i
sw
t
ri
t
2
• Extra energy dissipation in Sw
0
because of lengthened voltage
fall time.
t + t
ri rr
Energy dissipation
W /
W
total base
W /W
base
WT = d is s ipat ion in
R
0.4
W /
s witc h S w
W
T base
0.2
Io t fi
Cs 1 =
0
2 Vd
0 0.2 0.4 0.6 0.8 1 1.2 1.4
C /C
s s1
Wtota l = W R + W T
i
sw
Wb as e = 0 .5 V d Io t fi
I
o
v
V sw
d
Selection of Cs
• Minimize WR + WT
Vd
• Limit icap(0+) = R < Irr
s
Vd
• Usually designer specifies Irr < 0.2 Io so Rs = 0.2 Io
kV
d
i
+
f
I
R
ov
s
o
w
Io
V
d
V
d
S D
w ov
- C
v
s
ov
w
o t
fi
• Step-down converter with
overvoltage snubber comprised of
Dov, Cov, and Rov. • Sw it ch S w wav e for ms w it hout ov e rvo lta g e sn ubb e r
kV d tfi
• Lσ =
Io
Copyright © by John Wiley & Sons 2003 Snubbers - 15
Operation of Overvoltage Snubber
i
L σ
π LσCov
• Dov on for 0 < t <
L
2
σ
+
π LσCov
R
D
ov
ov
• tfi <<
V 2
d
+ i
- +
L +
+ +
σ v (0 ) =V i (0 )=I
L σ o
V Cov d
v
d C
Cov
ov
off.
• Df forced to be on Δ V
sw,max
i
of Sw. 2 2
C ( Δ V ) L (I )
ov sw,max σ o
v
=
s
2 2
w
π
L C
σ ov
0
Snubbers - 16
Overvoltage Snubber Design
Ls Io 2
• Cov =
( Δvsw,m ax) 2
• Limi t Δvsw,m ax t o 0 .1 V d
kV d tfi
• Using L s = in eq uation for Cov yield s
Io
tfiIo
• Cov = 20 0 k Cs1 whe re Cs1 = w hich is use d
2V d
in turn-off snubbe r
Step-down converter
+
D
+
with turn-on snubber
D
I
f f
o
R
Ls
L
circuit Ls
inductor Ls.
R V
V d
L Ls
d s
D
f
D
-
S
w -
w
large.
i
sw
I
o
Without
With
snubber
snubber
sw
d is w
• con t rol le d b y s wit c h S w
dt V
a nd dr ive circui t . d
I
o
LsIo
• Δvsw =
tri i
t t
ri rr
w
I
v
d is w Vd Io
reduced
Vd t ri I
o
• Ls 1 =
Io
i
d is w w
dt
o
t ≈ > t + t
ri rr
on
I R
D o
I Ls
f I R exp(-R t/L )
o
o Ls Ls s
i
s
w V
I d
o
R
V Ls
L
d s
D s
t
Ls rv
S
- w
Se le ction o f indu c to r
• Larger Ls decreases energy dissipation in switch at turn-on
• Wsw = WB (1 + Irr/Io)2 [1 - Ls/Ls1]
• WB = VdIotfi/2 and Ls1 = Vdtfi/Io
• Ls > Ls1 Wsw = 0
1 3 5
v L
- an + σ
bn
B i
d
C
s
4 6 2
R
s
Phase-to-neutral waveforms α
v
bn
v
an
• v LL( t ) = 3 Vs s in( ωt - 60 °)
3
• Maxim um rms line -to-line voltag e V LL = Vs
2
v = v v ω t
v =
LL 1
bn an
ba
Assumptions
⎡ I ⎤2
⎢ rr⎥
• Snub b e r c a p a cit or Cs = C b a s e = L σ ⎢ ⎥
⎣V d ⎦
d iLσ
• From s nubb e r eq uival
e nt circuit 2 Lσ = 2 V LL
dt
d iLσ 2 V LL 2 V LL
• Irr = trr = t rr = t = 25 ωIa1 trr
dt 2 Lσ 0.05 V LL rr
2
3 I a1 ω
• V d = 2 V LL
0.05 V LL ⎡
⎢25 ωIa1 trr⎤
⎥
2 8.7 ωIa1 trr
• Cs = Cbase = ⎢ ⎥ =
3 I a1 ω ⎣ 2 V LL ⎦ V LL
V d
• Snub b e r re sistance R s = 1.3 R base = 1.3
Irr
2 V LL 0.07 V LL
• Rs = 1.3 =
25 ωIa1 trr ωIa1 trr
LσIrr2 CsV d 2
• WR = + = 18 ω Ia1 V LL( t rr) 2
2 2