Architecture of MOSFET

• Four Terminals:
– Drain (D), Gate (G), Body (B), and source
(S).
• Body and Source are Connected
To ensure that the body diodes are always
Reverse Biased.
• Three modes:
• Cutoff (Off-Swtich), Triode (Resistor),
Saturation (VCCS)

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 MOS Capacitances
• Any two conductors CG = CoxWL
separated by an insulator
form a parallel-plate Cox is unit gate oxide capacitance
capacitor.
• Gate Capacitance is very Overlap
Poly Gate
important as it creates
channel charge necessary Source Drain
for operation xd xd
n+ W n+
• Source and Drain have
capacitance to body across
Ldrawn
reverse-biased diodes called
Diffusion Capacitance
because it is associated with tox
source/drain diffusion
n+ n+
Leff

- 5/49
 Diffusion Capacitance of Transistor
Channel-Stop
Implant (NA+)

W source
Bottom Plate
Junction Depth xj (ND)
Channel
Substrate (NA)
Side Walls
LS

Cdiff = Cbp + Csw = Cj (Area of Source)+ Cjsw (Perimeter Source Sidewalls)

= Cj LS W + Cjsw (2LS + W)

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NMOS and PMOS Operation

For VGS < Vtn no channel formed; transistor in

cutoff iD= 0
For VGS > Vtn channel is induced; transistor
operates in saturation or triode region depending
on whether channel is continuous or pinched off
at the drain

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 Transistor Characteristics
1) If the width of a transistor increases, the current will
increase decrease not change
2) If the length of a transistor increases, the current will
increase decrease not change
3) If the supply voltage of a chip increases, the maximum transistor
current will
increase decrease not change
4) If the width of a transistor increases, its gate capacitance will
increase decrease not change
5) If the length of a transistor increases, its gate capacitance will
increase decrease not change
6) If the supply voltage of a chip increases, the gate capacitance
of each transistor will
increase decrease not change
6) If the width of a transistor increases, its resistance will
increase decrease not change

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 CS Amp as an INVERTER

Cut-off

Saturation

Triode

• Large Signal Characteristics shows that CS amp is an

inverter.
• Vout = VDD when Vin < Vth
• Vout = (VDD - IdRd) i.e Low, when Vin = High
• This is a INV behavior , when we are in cut-off & Triode
• It behaves as amplifier when in saturation
• Problem: When Vin is high, the current flows all the time. In case of
million of inverters, the total current becomes very large.
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 CS Amp as an INVERTER
Example:
Cut-off

Saturation

Find the Vout when Vin=0 and Vin Triode

=1.4V

Solution
• Vin = 0V ;
• VGS ≤ Vtn its cutoff region ; ID =0 ; and Vout = (VDD - IdRd) Therefore, Vout = (VDD - IdRd) =
0
• Vin = 1.4V ; VGS > Vtn (It can be triode or saturation)
• Assume Saturation, ID = Kn/2 (Vov)2 = 2(1)2 = 2mA ; Vout = (VDD - IdRd) = 1.8-35 = -33.2V,
this is not possible, so the transistor is in triode.
• Assume triode now ID = Kn(VdsVov) , it will make a quadrature equation and one
root will be a valid value.
• See ID flows all the time, when Vin = 1V.

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 CMOS Inverter
• NMOS microprocessors (made of NMOS
transistors only) were dissipating as
much as 50 W and alternative design
technique was needed.
• CMOS solves the continuous current
flow problem.
• CMOS, needs both PMOS and NMOS
devices for their logic gates to be
realized
• The concept of CMOS was introduced in
1963 by Wanlass and Sah, but it did
not become common until the 1980’s.
• CMOS dominates all type of digital IC
design today.

Section 2.5 Weste Book, 4th Edition.

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 Vin-Vout Characteristic of CMOS INV
• The Vout changes when Vin changes from 0 to Vdd.
• The NMOS and PMOS current is equal.
• The size of the NMOS and PMOS are equal in this case. bp / bn = 1,
switching point will be at VDD/2

A
B

• VDD/2 C

• VDD/2

D E

Linear or Triode or Restive region is same

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 Noise Margins
• Noise Margin (NM) is the amount by which the signal exceeds the
threshold for a proper '0' or '1'.

-
 Noise Margins
• To maximize noise margins, select logic levels at unity gain point of
DC transfer characteristic

Desired Region
of Operation

Desired Region
of Operation

-
 Skew Gate. Why we need it?
• If bp / bn  1, switching point will move from VDD/2

• An unskewed gate has equal noise

margins
• Increasing (decreasing) PMOS width
to NMOS width increases (decreases)
the low noise margin and decreases
(increases) the high noise margin
This is static behaviors, what
• Using the unequal NMOS/PMOS size
happens when the pulse is
we can adjust to desired NMs
applied? Delay!

-
 Definitions: Rise, Fall and Prop. Delay
• tpdr: Rising Propagation Delay
– From input to rising output
crossing VDD/2
• tpdf: Falling Propagation Delay
– From input to falling output
crossing VDD/2
• tpd: Average Propagation Delay
– tpd = (tpdr + tpdf)/2
• tr: Rise Time
– From output crossing 0.2 VDD
to 0.8 VDD
• tf: Fall Time
– From output crossing 0.8 VDD
to 0.2 VDD

-
 Definitions: Contamination Delay
• tcdr: Rising contamination delay
– From input to rising output crossing VDD/2
• tcdf: Falling contamination delay
– From input to falling output crossing VDD/2
• tcd: Average Contamination Delay
– tpd = (tcdr + tcdf)/2

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 Inverter Sizing
• Width of NMOS
and PMOS is
selected to achieve
equal resistance.
This will make the
rise and fall time
almost equal.
• Electrons has
mobility ~2.7
times higher than
holes.
• Thus PMOS ~ 2 to
3 times to the
NMOS size.
• Length is chosen
minimum (Lmin) to
attain higher fT

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 NMOS and PMOS RC Model
• Use equivalent circuits for MOS transistors
• Ideal switch + capacitance and ON resistance
• Unit NMOS has resistance R, capacitance C
• Unit PMOS has resistance 2R, capacitance C
• Capacitance proportional to width of transistor
• Resistance inversely proportional to width of Transistor

d
s
kC
kC
R/k
d 2R/k
d
g k g kC
g k g
s kC kC
kC s
s
d

We roughly estimate C for a minimum length transistor to be 1 fF/μm of width. In a

65 nm process with a unit transistor being 130nm wide, C is thus about 0.1 fF.
Section 4.3.4 Weste Book, 4th Edition.

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 Transient Step Response of RC
• The propagation delay is the time at which Vout reaches VDD /2.
• τ = RC. , The output reaches 50% at RCln2. while ln 2 = 0.69
• 0.69RC is estimated delay , this is first order approximation

• Effective Delay tpd = RC

-
 RC Equivalent circuit of Inverter
• Inverter equivalent circuit nMOS transistor of unit size and a pMOS transistor of
twice the unit size to attain the same resistance R.
• If the input A rises, the nMOS transistor will be ON and the pMOS OFF.
• If the input A rises, the nMOS transistor will be ON and the pMOS OFF.
• The total capacitance on the output Y is 3C.
• Delay = 3RC, also called unit delay. • Diffusion capacitanceof
source and drain and
channel resistance is
modeled in this simple
model.
• All the transistor parasitic
capacitances change with
the mode of operation,
here we assume that the
are fixed and not
changing, specially we
assume the single value at
the transition edge.
• Beside this simplicity, this
is close to the actual
simulation you are doing
in LAB using BSIM models.

Section 4.3.4 Weste Book, 4th Edition.

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 Eq Circuit of Loaded INV
• Inverter equivalent circuit for a fanout-of-1 inverter with negligible wire capacitance.
• nMOS transistor of unit size and a pMOS transistor of twice unit size.
• If the input A rises, the nMOS transistor will be ON and the pMOS OFF (FigC).
• The capacitors shorted between two constant supplies are also removed because they are
not charged or discharged.
• The total capacitance on the output Y is 6C. , and delay is 6RC.

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Inverter Delay Estimation

-
 Elmore Delay

The function has two real poles and the step response is

Further approximated as a first order system

with a single time constant:

R1 R2 R3 RN
Elmore delay of RC ladder:
C1 C2 C3 CN

t pd  R
nodes i
i to  source Ci

 R1C1   R1  R2  C2  ...   R1  R2  ...  RN  CN

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 Fan-in and Fan-out Inverter

Fan-in M

Fan-out h

td = (R/w)(3wc+3mc) H
= RC (3 + 3m/w)
= RC (3 + 3h) , as h=m/w

-
65 nm Inverter Delay

td = RC (3 + 3h)
= (10K. 0.1fF) (3 +3.4)
= 1ps (15) = 15ps

-
 Ring Oscillator Frequency
Unit transistor R = 10K ohms and C = 0.1 fF in a 65 nm process, compute the delay.

• td = 3RC = 3(10K. 0.1fF) = 3ps Ring Oscillator are used during

• An N-stage ring oscillator has a period of 2N wafer testing to measure the effects
stage delays because a value must propagate of manufacturing process
variations. Ring oscillators can also
twice around the ring to regain the original
be used to measure the effects of
polarity.
voltage and temperature on a chip.
• T = 2 × 2N (td) One of the inverters should be
• f = 1/T = 1/4N (td) = 1/ (4x 31x 3ps) = 2.7GHz replaced with a NAND gate to turn
the ring off when not in use to save
• What is mistake? The FO is not considered, the
power.
actual delay of one INV is 6ps