Timing Paths: Continued

DAY-8
Timing Paths
continued…
1
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Recap of Timing…
• Setup time - The minimum amount of time the data signal should be stable before the clock
edge for reliable sampling of data
• Hold time - The minimum amount of time the data signal should be stable after the clock edge
for reliable sampling of data
• Meeting both setup and hold time requirements is mandatory
• This requirement makes sure that proper(correct) data is captured and there is no metastable
state data in the design
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Timing concepts explained…
• Critical path - The path between an input and an output with the maximum delay
• Arrival time - The time elapsed for a signal to arrive at a certain point. To calculate the arrival
time, delay calculation of all the components in the path will be required
• Required time - The latest time at which a signal can arrive without making the clock cycle
longer than desired
• Clock Latency - The total delay that the clock signal takes between any two points
• Slack - The difference between the required time and the arrival time, it is associated with each
connection
• Metastability - It is a state which is unpredictable, when there is setup and hold violations.At
the end of metastable state, the flip-flop settles down to either '1' or '0‘
Setup Analysis (Max Delay
Analysis)
• The setup check is one of the checks that will ensure that data launched at UFF0 is
captured at UFF1 in given time period
• Setup check ensures that data does not go to metastable state
• Setup Slack = Required Time – Arrival Time

• Required Time = Clock period + Capture clock latency –Setup_req - Clock Uncertainty
• Arrival Time = Launch clock latency + Tck-q +Data_path Delay

Continued…
• For the data to be safely captured at UFF1 Setup Slack > = 0
• Required Time: Capture Clock path gives required time, as shown in Figure, it is time
taken by clock signal to reach end point from source is defined as required time
• Arrival Time: Data path starting from launch Clock provides actual arrival path as shown
in Figure. Thus, time taken by data signal to reach end point is defined as arrival time
P is the Time period or one clock cycle

Example of Setup timing report

Hold Analysis (Min Delay Analysis)
• The Hold check is one of the checks that will ensure that data launched at clock edge 1 of UFF0
is not captured at clock edge 1 of UFF1 but captured at clock edge 2 of UFF1
• Hold check ensures that the design does not move to the next state before its stipulated time;
i.e., the design retains its present state only
• The hold check should be one active edge prior to the one at which setup is checked, unless there
are some architectural care-abouts in the state machine design
• Hold Slack = Arrival Time – Required Time

• Required Time = Thold + Tskew
• Arrival Time = TCL(Total combinational delay) + Tck-q

Continued…

Example of Hold timing report

Jitter
• Jitter is the timing variations of a set of signal edges from their ideal values
• Clock Jitter is the deviation of the clock edge with ideal clock as a reference
• Jitter is one edge(rise/fall) movement/deviation from its ideal position with reference as other
edge(rise/fall)

Clock
Jitter
• How will clock jitter affect STA?
• Clock Jitter affects the clocks time period. Clock period may increase or decrease
• Going back to our setup time equation. Change in clock period effects setup slack
• Increase in clock period helps setup and decrease in clock period reduces setup slack
• Setup Slack = Required Time – Arrival Time
= (Clock period + Capture clock latency –Setup ) – (Launch clock latency + Tck-q +Datapath Delay)
• For Hold Analysis the check happens at same edge ,so the clock period remains 0.So, Jitter
does not effect hold

Uncertainty
• How do we model the clock jitter in our timing environment?
• Clock jitter is modelled as clock uncertainty

• For setup - the subsequent clock edge can come between -100ps to +100ps of the ideal
subsequent edge , -100ps being the bounding (pessimistic) condition for setup
100ps should be accounted as part of setup uncertainty
• For Hold - the check happens at the same edge so no effect of jitter. So, nothing to be
accounted for jitter as part of hold uncertainty
100ps

Clock Duty Cycle Distortion
• The distortion relative to the ideal clock of either the active high or active low portion of a clock
period is called duty cycle distortion(DCD).
• The time period may remain the same, but the duty cycle changes
Fall edge of the clock is shifted
Ideal Clock
Clock with DCD

Min. Time period and Min. Pulse width
• Min time period or one cycle time required to acquire a stable data for the succeeding stage
processing
• To satisfy the minimum Time period, minimum pulse width must be met
• Min pulse width check is to ensure that pulse width of clock signal is more than required
value

Minimum pulse width violation example
STA problem: Consider below figure, wherein minimum pulse width requirement of a flip-flop is
590 ps. It is getting clocked by a PLL of 500 MHz with a duty cycle variation of 60 ps. There are 30
buffers in clock path, each having a rise delay of 60 ps and fall delay of 48 ps. Will this setup be able
to meet the duty cycle requirement of flip-flop? Find the slack available.

Solution:
Here, we must remember that pulse can be either high pulse or low pulse. So, we need to check
for both. Let us start with high pulse:
Pulse width check for high pulse: Here, we are left with calculating the latest possible arrival of rising edge
and earliest possible arrival of falling edge at the flip-flop. It is given that
Ideal clock period = 2000 ps (500 MHz frequency)

Ideal half cycle = 1000 ps
Duty cycle variation of clock source = 60 ps
So, if we assume that positive edge of the clock has arrived at 0-time, negative edge can arrive at any time
between 940 ps (1000 - 60) and 1060 ps (1000 + 60). Taking the pessimistic case, we have to assume negative
edge arrives at 940 ps thereby making the high pulse as 940 ps at clock source.
Now, there are 30 buffers with rise delay of 60 ps and fall delay of 48 ps.
Rising edge will reach flip-flop at time (0 + 30 * 60) = 1800 ps.
Falling edge will reach flip-flop at time (940 + 30 * 48) = 2380 ps
Effective pulse width visible at flip-flop = 2380 - 1800 = 580 ps
Now, the pulse width requirement = 590 ps
Slack = Actual pulse width = Required minimum pulse width = -10 ps
So, we are violating the minimum high pulse width requirement by 10 ps.

Pulse width requirement for low pulse: Similar to the earlier case, we have to find the
difference in arrival of latest negative edge and earliest positive edge.
Ideal clock period = 2000 ps (500 MHz)

Ideal half cycle = 1000 ps
Duty cycle variation of clock source = 60 ps
If we assume that negative edge arrived at 0 ps, positive edge can arrive at any time between 940
ps and 1060 ps. Taking the pessimistic case, low pulse width = 940 ps at clock source.
Now, there are 30 buffers with rise delay of 60 ps and fall delay of 48 ps.
Falling edge will reach flip-flop at time (0 + 30 * 48) = 1440 ps

Rising edge will reach flip-flop at time (940 + 60 * 30) = 2740 ps
Effective pulse width visible at flip-flop = 2740 - 1440 = 1300 ps
Pulse width requirement = 590 ps

Slack = 1300 - 590 = 710 ps
So, we are meeting the low pulse width requirement by 710 ps.
Keep Practicing & Exploring…
THANK YOU

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DAY-8

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• Setup Slack = Required Time – Arrival Time

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P is the Time period or one clock cycle

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• Hold Slack = Arrival Time – Required Time

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• Clock jitter is modelled as clock uncertainty

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Fall edge of the clock is shifted

Clock with DCD

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Ideal clock period = 2000 ps (500 MHz frequency)

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Ideal clock period = 2000 ps (500 MHz)

Falling edge will reach flip-flop at time (0 + 30 * 48) = 1440 ps

Pulse width requirement = 590 ps

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