Digital System Design

KEC302

Unit-3
Synchronous Sequential
Circuits

Deepak Sigroha
Electronics Engineering Department
Rajkiya Engineering College Sonbhadra
deepak.sigroha@recsonbhadra.ac.in
+91-9478856526
 Outline
Looping
• Synchronous Sequential Circuits
• Analysis of Sequential Circuits
• Finite State Machine Model
• Mealy and Moore FSM
• State Reduction and Assignment
• Design Procedure
 Combinational Circuits

 Consists only of logic gates.

 The output are determined by the present value of input.
 Circuit behavior specified by a set of Boolean functions, Truth-tables, and K-maps.
 We have learned techniques to analyze and synthesize such circuits.
 Examples: Adder, Multiplexers, Encoders, Decoders, etc.
Unit 3 – Synchronous Sequential Circuits and Systems (FSM) 3
 Sequential Circuits
 Consists of logic gates and
storage elements
 The output are determined by the
present value of the input and the
state of the storage elements
 In effect, the output may depend
on past values of the input via the
state of the storage elements
 Circuit behavior specified by
timed sequence of input and Present State Next State
internal states via state machines Information Information

Unit 3 – Synchronous Sequential Circuits and Systems (FSM) 4

 The Finite State Model
 A finite state machine is an abstract model describing the synchronous
sequential machine.
 The behavior of a finite state machine is described as a sequence of events
that occur at discrete instants designated as t = 1, 2, 3 ... etc.
 Suppose that the machine has been receiving input signals and also
responding by producing output signals.
 If, now at time t, we were to apply an input signal x(t) to the machine, the
response z(t) would depend on x(t) as well as on the past inputs to the
machine, and since a given machine might have an infinite varieties of
possible histories, it would need an infinite capacity for storing them.
 Since in practice, it is impossible to implement machines which have infinite
storage capabilities, we will concentrate on those machines whose past
histories can affect their future behavior only in a finite number of ways.
These are called the finite state machines, that is, machines with a fixed
number of states.
 These machines can distinguish among a finite number of classes of input Block diagram of a finite state model.
histories.
 These classes of input histories are referred to as the internal states of the
machine. Every finite state machine, therefore, contains a finite number of
memory devices.
Unit 3 – Synchronous Sequential Circuits and Systems (FSM) 5
 Analysis of Sequential Circuits
 Analysis describes what a given
circuit will do under certain
operating conditions.

Unit 3 – Synchronous Sequential Circuits and Systems (FSM) 6

 Representation of Sequential Circuits
How do we specify a combinational circuit?

Output variables as a function of input variables, using

1. natural language,
2. logic gates,
3. Boolean expressions, and
4. Truth-tables or K-maps.
How do we specify a clocked sequential circuit?

Output variables as a function of input variables, using

5. natural language OK.
6. logic gates OK.
7. Boolean expressions, Wait a minute!
8. Truth-tables or K-maps. Wait a minute!
Unit 3 – Synchronous Sequential Circuits and Systems (FSM) 7
 Clocked Sequential Circuits
How to express clocked sequential circuits using Boolean expressions.

 How clocked sequential circuits are different?

 Due to storage elements that introduce state variables
 State variables act both as input and output variables
 Output variables may depend on both the input variables and current value of state variables
 The next value of state variables may also depend on input variable and the current value of the state
variable

Solution

 We need two copies of a state variable A— present-state variable representing the present value of and
next-state variable representing the value of one clock-edge later
 Specify output variables and next-state variables as function of input variables and present-state variables.
Unit 3 – Synchronous Sequential Circuits and Systems (FSM) 8
 Analysis of Sequential Circuits
The behavior of a clocked sequential circuit is determined from
 The inputs
 The outputs
 The state of its flip-flops
 The outputs and the next state are both a function of the inputs and the present state

To analyze a sequential circuit, we can use

 State equations
 State table
 State diagram
 Flip-Flop input equations

Unit 3 – Synchronous Sequential Circuits and Systems (FSM) 9

 Clocked Sequential Circuits: State Equations
 Specify the next state as a function of the present state
and inputs
 Also called transition equation
 Analyze the combinational part directly.
 State Equations or transition equations.

 To simplify, we omit from the right hand side, and write:

 Similarly, the present-state value of the output can be

expressed algebraically as

 By removing the symbol from present state:

Unit 3 – Synchronous Sequential Circuits and Systems (FSM) 10

 Clocked Sequential Circuits: State Tables
 Enumerate the time sequence of inputs, State table for , and
outputs, and flip-flop states
 Also called transition table
 Similar to list the truth table of state
Present State Input Next state Output
equations
A B x A B y
 Consist of four sections
0 0 0 0 0 0
 Present state,
 Input, 0 0 1 0 1 0
 Next state, and 0 1 0 0 0 1
 Output 0 1 1 1 1 0
 A sequential circuit with m flip-flops and n 1 0 0 0 0 1
inputs need rows in the state table.
1 0 1 1 0 0
1 1 0 0 0 1
1 1 1 1 0 0

Unit 3 – Synchronous Sequential Circuits and Systems (FSM) 11

 Clocked Sequential Circuits: State Tables
 It is sometimes convenient to express the state table in a slightly different form having only three
sections:
 Present state,
 Next state, and
 Output.
 The input conditions are enumerated under the next-state and output sections
State table for , and

Present State Next State Output

x=0 x=1 x=0 x=1
A B A B A B y y
0 0 0 0 0 1 0 0
0 1 0 0 1 0 1 0
1 0 0 0 1 0 1 0
1 1 0 0 1 0 1 0
Unit 3 – Synchronous Sequential Circuits and Systems (FSM) 12
 Clocked Sequential Circuits: State Diagram
 Graphically represent the information in a Present Next State Output
state table State x=0 x=1 x=0 x=1
 Circle: a state (with its state value inside)
 Directed lines: state transitions (with A B A B A B y y
inputs/outputs above) 0 0 0 0 0 1 0 0
 Ex: starting from state 00 0 1 0 0 1 1 1 0
 If the input is 0, it stays at state 00 with 1 0 0 0 1 0 1 0
output=0
1 1 0 0 1 0 1 0
 If the input is 1, it goes to state 01 with
output=0 0/0 1/0
 The state table is easier to derive from a 00
0/1
10
given logic diagram and state equations
 The state diagram is suitable for human

1
1/0 0/1

0/
1/0
interpretation

01 11
1/0
Unit 3 – Synchronous Sequential Circuits and Systems (FSM) 13
 Clocked Sequential Circuits: Input Equations
 To draw the logic diagram of a sequential circuit, we need
 The type of flip-flops
 A list of Boolean expressions of the combinational circuits
 The Boolean functions for the circuit that generates external outputs is called output equations.
 The Boolean functions for the circuit that generates the inputs to flip-flops is flip-flop input
equations.
 Sometimes called excitation equations.
 The flip-flop input equations provide a convenient form for specifying the logic diagram of a
sequential circuit.

Unit 3 – Synchronous Sequential Circuits and Systems (FSM) 14

 Clocked Sequential Circuits: Input Equations
 We call the D-input of a flip-flop whose
output is labeled with symbol S.
 The input equation for is

 Combining the input equation with the

characteristic equation of the flip-flop will give
the next-state equation. Consider

 This is because of the characteristics equation

that equates the next state to the value of D input:

Unit 3 – Synchronous Sequential Circuits and Systems (FSM) 15

 Clocked Sequential Circuits: Input Equations
 Here the input equations for and are

 Combining the input equation with the

characteristic equation of the flip-flop
will give the next-state equation.
Consider

Unit 3 – Synchronous Sequential Circuits and Systems (FSM) 16

 Analysis of Sequential Circuits

Circuit Diagram Sate Equations State Table State Diagram

Unit 3 – Synchronous Sequential Circuits and Systems (FSM) 17

 Analysis with D Flip-Flops
 Input equation PS Input NS
A x y A

0 0 0 0
 State Equation
0 0 1 1
0 1 0 1
0 1 1 0
1 0 0 1
1 0 1 0
1 1 0 0
1 1 1 1
(b) State table

Unit 3 – Synchronous Sequential Circuits and Systems (FSM) 18

 Analysis with Other Flip-Flops
Method 1
 The sequential circuit using other flip-flops such as SR, JK or T type can be analyzed as follows:
1. Determine the flip-flop input equations in terms of the present state and input variables.
2. List the binary values of each input equation.
3. Use the corresponding flip-flop characteristic table to determine the next state values in the state table.

Method 2
 The next-state values can also be obtained by evaluating the state equations from the
characteristic equation. This is done by using the following procedure:
1. Determine the flip-flop input equations in terms of the present state and input variables.
2. Substitute the input equations into the flip-flop characteristic equation to obtain the state equations.
3. Use the corresponding state equations to determine the next-state values in the state table.

Unit 3 – Synchronous Sequential Circuits and Systems (FSM) 19

 Analysis with JK Flip-Flops
 Input equations PS Input NS Flip-Flop Inputs
A B x A B
0 0 0 0 1 0 0 1 0
0 0 1 0 0 0 0 0 1
0 1 0 1 1 1 1 1 0
0 1 1 1 0 1 0 0 1
1 0 0 1 1 0 0 1 1
1 0 1 1 0 0 0 0 0
1 1 0 0 0 1 1 1 1
1 1 1 1 1 1 0 0 0

Unit 3 – Synchronous Sequential Circuits and Systems (FSM) 20

 Analysis with JK Flip-Flops
 Input equations PS Input NS
A B x A B
0 0 0 0 1
 State equations 0 0 1 0 0
0 1 0 1 1
0 1 1 1 0
1 0 0 1 1
1 0 1 1 0
1 1 0 0 0
1 1 1 1 1

Unit 3 – Synchronous Sequential Circuits and Systems (FSM) 21

 Analysis with T Flip-Flops
 Input and output equations PS Input NS Outpu
t
A B x A B y
0 0 0 0 0 0
 State equations 0 0 1 0 1 0
0 1 0 0 1 0
0 1 1 1 0 0
1 0 0 1 0 0
1 0 1 1 1 0
1 1 0 1 1 1
1 1 1 0 0 1

Unit 3 – Synchronous Sequential Circuits and Systems (FSM) 22

 Mealy and Moore Models of Finite State Machines
 Mealy model:
 The output is a function
of both the present state
and input.
 The output may change if
the inputs change during
a clock cycle.

 Moore model:
 The output is a function
of the present state only.
 The output are
synchronized with the
clock.

Unit 3 – Synchronous Sequential Circuits and Systems (FSM) 23

 Memory Elements
 D Flip Flop

Unit 3 – Synchronous Sequential Circuits and Systems (FSM) 24

 Memory Elements
 T Flip Flop

Unit 3 – Synchronous Sequential Circuits and Systems (FSM) 25

 Memory Elements
 SR Flip Flop

Unit 3 – Synchronous Sequential Circuits and Systems (FSM) 26

 Memory Elements
 JK Flip Flop

Unit 3 – Synchronous Sequential Circuits and Systems (FSM) 27

 State Reduction
 The reduction in the number of flip-flops in a sequential circuit is
referred to as the state-reduction problem.
 Reducing the number of states in a state table, while keeping the external
input-output requirements unchanged.
 Example:
 Total 7 states
 There are an infinite number of input sequences that may be applied to the
circuit; each results in a unique output sequence.
 Consider input sequence 01010110100 starting from the initial state a.

State a a b c d e f f g f g a
Input 0 1 0 1 0 1 1 0 1 0 0
Output 0 0 0 0 0 1 1 0 1 0 0

Unit 3 – Synchronous Sequential Circuits and Systems (FSM) 28

 State Reduction
 Two states are said to be equivalent if, for each member of the set of
input, they give exactly same output and send the circuit either to same
state or to an equivalent state.
 When two states are equivalent, one of them can be removed without
changing the function of the circuit.
 It is difficult to tell whether two states are equivalent, but slightly easy to
tell when they are not equivalent.
Present State Next State Output
x=0 x=1 x=0 x=1
a a b 0 0
b c d 0 0
c a d 0 0
d e f 0 1
e a f 0 1
f g f 0 1
g a f 0 1
Unit 3 – Synchronous Sequential Circuits and Systems (FSM) 29
 State Reduction
 Two states are said to be equivalent if, for every possible inputs, they give exactly the same
output and have equivalent next state.

PS Next State Output PS Next State Output PS Next State Output

x=0 x=1 x=0 x= x=0 x=1 x=0 x=1 x=0 x=1 x=0 x=1
a a b 0 0 a a b 0 0 a a b 0 0
b c d 0 0 b c d 0 0 b c d 0 0
c a d 0 0 c a d 0 0 c a d 0 0
d e f 0 1 d e f 0 1 d e d 0 1
e a f 0 1 e a f 0 1 e a d 0 1
f g f 0 1 f e f 0 1
g a f 0 1

delete state g and replaced with delete state f and replaced with state d
state e

Unit 3 – Synchronous Sequential Circuits and Systems (FSM) 30

 State Reduction
 After reduction, the circuit has only 5 states with same input/output requirements.
PS Next State Output
x=0 x=1 x=0 x=1
a a b 0 0
b c d 0 0
c a d 0 0
d e d 0 1
 Original output sequence: e a d 0 1

State a a b c d e f f g f g a
Input 0 1 0 1 0 1 1 0 1 0 0
Output 0 0 0 0 0 1 1 0 1 0 0

 Reduced output sequence:

State a a b c d e d d e d e a
Input 0 1 0 1 0 1 1 0 1 0 0
Output 0 0 0 0 0 1 1 0 1 0 0 Reduced state diagram
Unit 3 – Synchronous Sequential Circuits and Systems (FSM) 31
 State Assignment
 Assign coded binary values to the states for State Assignment 1 Assignment 2 Assignment 3
physical implementation. Binary Gray Code One-Hot

 For a circuit with m states, the codes must a 000 000 00001

contain n bits where . b 001 001 00010

c 010 011 00100
 Assign unique binary values to states.
d 011 010 01000
 Three possible binary state assignments: e 100 110 10000
 Binary: assign the states in binary order
 Typical method without other considerations  Unused states are treated as don't care
 Gray code: assign the states by gray code conditions during the design.
 Lower power consumption during state transitions (if in
 Don't cares can help to obtain a simpler circuit.
order)
 One-hot: assign a specific flip-flop for each state  Sometimes don’t care condition may lead to
failure (severe problem, misshaping, danger,
 Simplify the circuit design but may have larger
hardware cost
accident etc.) of designed system.
 Example: Automatic Traffic Light System.
 So unused condition are treated as output=0.

Unit 3 – Synchronous Sequential Circuits and Systems (FSM) 32

 State Assignment
 Table 1 is the reduced state table of reduced sated diagram.
 Table 2 is the reduced state table with binary assignment1 substituted for the letter symbols of
the states.

Table2:
Table1: Reduced State Table with
Reduced State Table Binary Assignment 1
PS Next State Output PS Next State Output
x=0 x=1 x=0 x=1 x=0 x=1 x=0 x=1
a a b 0 0 000 000 010 0 0
b c d 0 0 001 010 011 0 0
c a d 0 0 010 000 011 0 0
d e d 0 1 011 100 011 0 1 Reduced state
diagram
e a d 0 1 100 000 011 0 1
Unit 3 – Synchronous Sequential Circuits and Systems (FSM) 33
 Synthesis of Sequential Circuits
 The procedure for designing synchronous sequential circuits:
1. From the word description and specification of the desired operation, derive a state diagram for the
circuit.
2. Reduce the number of states if necessary.
3. Assign binary values to the states.
4. Obtain the binary-coded state table.
5. Choose the type of flip-flops to be used.
6. Derive the simplified flip-flop input equations and output equations.
7. Draw the logic diagram.
 Step 4 to 7 can be automated
 Use HDL synthesis tools

Unit 3 – Synchronous Sequential Circuits and Systems (FSM) 34

 Example-1 (Sequence Detector)
Design a circuit that detects 3 or more consecutive 1’s at inputs or detects three 1’s at inputs (overlapping is allowed).
 Step1 : State Diagram

0/0 0/0
1/0
S0 S1
0

1/0
0/

S2
1/1

a) Mealy Machine

Unit 3 – Synchronous Sequential Circuits and Systems (FSM) 35

 Example-1 (Sequence Detector)
 Step3 : State Assignment

0/0 0/0 0/0 0/0

1/0 1/0
00 01 001 010
0

0
1/0 1/0
0/

0/
10 100
1/1 1/1

a) Mealy machine with Binary Assignment c) Mealy machine with One-Hot Assignment

Unit 3 – Synchronous Sequential Circuits and Systems (FSM) 36

 Example-1 (Sequence Detector)
 Step4 : Obtain Binary Coded State Table
State Table for Sequence Detector
Present State Input Next state Output
A B x A B y
0 0 0 0 0 0
0 0 1 0 1 0
0 1 0 0 0 0
0 1 1 1 0 0
1 0 0 0 0 0
1 0 1 1 1 0
1 1 0 0 0 1
1 1 1 1 1 1

Unit 3 – Synchronous Sequential Circuits and Systems (FSM) 37

 Example-1 (Sequence Detector)
 Step 5: Choose Flip-flops
 We need to store each state as a flip-flop such as D, J-K or T flip flops.
 We need to compute input logic for our flip-flops in order to properly change the state.
 The most common used flip-flop is of-course a D-flip-flop (Why?)
 A excitation table defines the logical properties of the input of a flip-flop in order to make a
desired change in the input.

P.S N.S Required Inputs

Qn Qn+1 S R J K D T
0 0 0 X 0 X 0 0
0 1
1 0 1 X 1 1
1 0
1 1 0 1 X 1 0 1
X 0 X
Unit 3 – Synchronous Sequential Circuits and Systems (FSM)
0 1 38
0
 Example-1 (Sequence Detector)
 Step 6: Using excitation table and state table, derive state table for corresponding flip-flop inputs.
 Using K-maps simplify the flip-flop input equations and the output equations.

D A ( A , B , x )=∑ ( 3,5,7 ) D A ( A , B , x )= Ax +Bx

State Table for Sequence Detector D B ( A , B , x )=∑ ( 1,5,7 ) D B ( A , B , x )= Ax +B ′ x
Present State Input Next state Output y ( A , B , x ) =∑ ( 6,7 ) y ( A , B , x ) = AB
A B x A (DA) B(DB) y
0 0 0 0 0 0
0 0 1 0 1 0
0 1 0 0 0 0
0 1 1 1 0 0
1 0 0 0 0 0
1 0 1 1 1 0
1 1 0 0 0 1
1 1 1 1 1 1

Unit 3 – Synchronous Sequential Circuits and Systems (FSM) 39

 Example-1 (Sequence Detector)
 Step 7: Draw the logic diagram.

Logic diagram of a Moore-type sequence detector

Unit 3 – Synchronous Sequential Circuits and Systems (FSM) 40
Example-1 (Sequence Detector) using JK Flip-Flop

State Table for Sequence Detector

PS Input NS FF Inputs Output
A B x A B JA KA JB KB y
0 0 0 0 0 0 X 0 X 0
0 0 1 0 1 0 X 1 X 0
0 1 0 0 0 1 X X 1 0
0 1 1 1 0 0 X X 0 0
1 0 0 0 0 X 0 0 X 0
1 0 1 1 1 X 0 1 X 0
1 1 0 0 0 X 0 X 0 1
1 1 1 1 1 X 1 X 1 1

Unit 3 – Synchronous Sequential Circuits and Systems (FSM) 41

 Example-1 (Sequence Detector) Using JK Flip-Flop
State Table for Sequence Detector
PS Input NS FF Inputs Output
A B x A B JA KA JB KB y
0 0 0 0 0 0 X 0 X 0
0 0 1 0 1 0 X 1 X 0
0 1 0 0 0 1 X X 1 0
0 1 1 1 0 0 X X 0 0
1 0 0 0 0 X 0 0 X 0
1 0 1 1 1 X 0 1 X 0
1 1 0 0 0 X 0 X 0 1
1 1 1 1 1 X 1 X 1 1

Unit 3 – Synchronous Sequential Circuits and Systems (FSM) 42

Example-1 (Sequence Detector) using JK Flip-Flop

Logic diagram of a
Moore-type sequence
detector
y =AB
Unit 3 – Synchronous Sequential Circuits and Systems (FSM) 43
 Example-2 (MOD-8 UP Counter) using T Flip-Flop
 Derive the state table with the excitation inputs.
 Other design procedures are the same.

State Table for MOD-8 Counter

Present Next State FF Inputs
State
A2 A1 A0 A2 A1 A0 TA2 TA1 TA0
0 0 0 0 0 1 0 0 1
0 0 1 0 1 0 0 1 1
3-bit UP Counter 0 1 0 0 1 1 0 0 1
State Diagram 0 1 1 1 0 0 1 1 1
1 0 0 1 0 1 0 0 1
1 0 1 1 1 0 0 1 1
1 1 0 1 1 1 0 0 1
1 1 1 0 0 0 1 1 1

Unit 3 – Synchronous Sequential Circuits and Systems (FSM) 44

 Example-2 (MOD-8 UP Counter) using T Flip-Flop
State Table for MOD-8 Counter
Present State Next State FF Inputs
A2 A1 A0 A2 A1 A0 TA2 TA1 TA0
0 0 0 0 0 1 0 0 1
0 0 1 0 1 0 0 1 1
0 1 0 0 1 1 0 0 1
0 1 1 1 0 0 1 1 1
1 0 0 1 0 1 0 0 1
1 0 1 1 1 0 0 1 1
1 1 0 1 1 1 0 0 1
1 1 1 0 0 0 1 1 1

Logic diagram of three-bit binary counter

Unit 3 – Synchronous Sequential Circuits and Systems (FSM) 45

 Example-3 (Sequence Detector)
Design a Mealy Type FSM that detects 1010 at inputs (overlapping is allowed).
 A sequence detector is a sequential machine which produces an output 1 every time the desired sequence is
detected and an output 0 at all other times.
 If the input sequence is 01101010 the corresponding output sequence is 00000101

Unit 3 – Synchronous Sequential Circuits and Systems (FSM) 46

Example-3 (Sequence Detector)

Unit 3 – Synchronous Sequential Circuits and Systems (FSM) 47

Example-3 (Sequence Detector)

Unit 3 – Synchronous Sequential Circuits and Systems (FSM) 48

 Example-3 (Sequence Detector)
Design a Mealy Type FSM that detects 1010 at inputs (overlapping is not allowed).
 A sequence detector is a sequential machine which produces an output 1 every time the desired sequence is
detected and an output 0 at all other times.
 If the input sequence is 0110101010 the corresponding output sequence is 0000010001

0/1
Present State Next State, Output (z)
x=0 x=1
A A, 0 B, 0
B C, 0 B, 0
C A, 0 D, 0
D A, 1 B, 0

Unit 3 – Synchronous Sequential Circuits and Systems (FSM) 49

 Example-3 (Sequence Detector)
Design a Moore Type FSM that detects 1010 at inputs (overlapping is allowed).
 A sequence detector is a sequential machine which produces an output 1 every time the desired sequence is
detected and an output 0 at all other times.
 If the input sequence is 01101010 the corresponding output sequence is 00000101

Unit 3 – Synchronous Sequential Circuits and Systems (FSM) 50

 Example-3 (Sequence Detector)
Design a Moore Type FSM that detects 1010 at inputs (overlapping is not allowed).
 A sequence detector is a sequential machine which produces an output 1 every time the desired sequence is
detected and an output 0 at all other times.
 If the input sequence is 0110101010 the corresponding output sequence is 0000010001

Present Next State Output

State
x=0 x=1 z

A A B 0
B C B 0
C A D 0
D E B 0
E A B 1

Unit 3 – Synchronous Sequential Circuits and Systems (FSM) 51

 Example-4 (Serial Binary Adder)
 The block diagram of a serial binary adder is shown in Figure.
 It is a synchronous circuit with two input terminals designated and which carry the two binary
numbers to be added and one output terminal which represents the sum.

Unit 3 – Synchronous Sequential Circuits and Systems (FSM) 52

Example-4 (Serial Binary Adder)

Unit 3 – Synchronous Sequential Circuits and Systems (FSM) 53

Example-4 (Serial Binary Adder)

Unit 3 – Synchronous Sequential Circuits and Systems (FSM) 54

 Example-4 (Serial Binary Adder)
 In a Moore type machine the output depends only on the present state of the machine.
 It does not depend on the input at all. We see that in a serial adder, the output in each state may
be 0 or 1 depending on the values of the inputs.
 So a Moore type state machine will need more than two states.

Unit 3 – Synchronous Sequential Circuits and Systems (FSM) 55

 Question (1)
 The state transition diagram for the logic
circuit shown in the following figure is

Unit 3 – Synchronous Sequential Circuits and Systems (FSM) 56

 Question (2)

Unit 3 – Synchronous Sequential Circuits and Systems (FSM) 57

 Question (3)
 The state diagram of a sequence detector is shown below. A. the sequence 01011 is
State is the initial state of sequence detector. If the output is detected.
1, then B. the sequence 01001 is
detected.
C. the sequence 01010 is
detected.
D. the sequence 01110 is
detected.

Unit 3 – Synchronous Sequential Circuits and Systems (FSM) 58

 References
1. T. L. Floyd, “Digital Fundamental”, 11th Ed., USA : Prentice-Hall.
2. R.J. Tocci, N. S. Widmer and G. L. Moss “Digital Systems: Principles and Applications”,
11th Ed., USA : Prentice-Hall.,
3. M. Morris Mano, M. D. Ciletti, “Digital Design” 6th Ed., USA : Prentice-Hall.
4. A. Anand Kumar, “Fundamentals of Digital Circuits” 4th Ed., PHI.
5. M. Morris Mano, Charles Kimi, “Logic and Computer Design Fundamentals” 4h Ed., USA :
Prentice-Hall.
6. William Kleitz, “Digital Electronics: A Practical Approach with VHDL” 9th Ed., USA :
Prentice-Hall.

Unit 3 – Synchronous Sequential Circuits and Systems (FSM) 59

Thank You