Hardwired and Micro programmed Control

Hardwired Control
To execute instructions, the processor must have some means of generating the control signals needed in the proper sequence. A wide variety of techniques are used to solve this problems and the approaches fall into one of two categories: 1. Hardwired Control, and 2. Microprogrammed Control.

Cont
In order to execute a single instruction, a sequence of control signals is required. Each step in this sequence is completed in one clock period. A counter may be used to keep track of the control steps. Each state, or count, of this counter corresponds to one control step. The required control signals are determined by the following information:

Control Unit Organization

Cont
Contents of the control step counter. Contents of the instruction register. Contents of the condition code flags. External input signals, such as MFC and interrupt requests. The figure above shows the structure of control unit. The decoder/encoder block is a combinational circuit that generates the required control outputs, depending on the state of all its inputs. i. ii. iii. iv.

Cont
The decoding and encoding functions can be separated to obtain a more detailed block diagram. The step decoder provides a separate signal line for each step, or time slot, in the control sequence. The output of the instruction decoder consists of a separate line for each machine instruction.

Separation of the Decoding and Encoding Functions

Cont
For any instruction loaded in the IR, one of the output lines, INS1 through INSn, is set to 1 and all other lines are set to 0. The input signals to the encoder block are combined to generate the individual control signals Yin, Pcout, Add, End and so on. The control hardware can be viewed as a state machine that changes from one state to another in every clock cycle, depending on the contents of the IR, the condition codes, and the external inputs.

Cont
The outputs of the state machine are the control signals. The sequence of operations carried out by this machine is determined by the writing of the logic elements, hence the name hardwired. A controller that uses this approach can operate at high speed but has little flexibility, and the complexity of the instruction set it can implement is limited.

A Complete Processor

Cont
The figure shows the block diagram of a complete processor. It has an instruction unit that fetches instructions from an instruction cache or from the main memory when the desired instruction are not already in the cache. There are separate processing units to deal with integer data and floating-point data. A data cache is inserted between these units and the main memory.

Cont
Separate caches are used for instructions and data. The processor is connected to the system bus and, hence, to the rest of the computer, by means of a bus interface.

MICROPROGRAMMED CONTROL Control Memory Microprogram

- Program stored in memory that generates all the control signals required to execute the instruction set correctly - Consists of microinstructions

Microinstruction
- Contains a control word and a sequencing word Control Word - All the control information required for one clock cycle Sequencing Word - Information needed to decide the next microinstruction address - Vocabulary to write a microprogram

Control Memory(Control Storage: CS)

- Storage in the microprogrammed control unit to store the microprogram

Writeable Control Memory(Writeable Control Storage:WCS)

- CS whose contents can be modified -> Allows the microprogram can be changed -> Instruction set can be changed or modified

Dynamic Microprogramming
- Computer system whose control unit is implemented with a microprogram in WCS - Microprogram can be changed by a systems programmer or a user

Sequencer (Microprogram Sequencer)

A Microprogram Control Unit that determines the Microinstruction Address to be executed in the next clock cycle - In-line Sequencing - Branch - Conditional Branch - Subroutine - Loop - Instruction OP-code mapping

ADDRESS SEQUENCING
Microinstructions are stored in control memory in groups, with each group specifying a routine. Each computer instruction has its own microprogram routine in control memory to generate the microoperations that execute the instruction. The hardware that controls the address sequencing of the control memory must be capable of sequencing the microinstructions within a routine and be able to branch from one routine to other. The steps that the control must undergo during the execution of a single computer instruction are: 1. An initial address is loaded into the CAR when power is turned on which is usually the address of the first microinstruction that activates the instruction fetch routine. The fetch routine is sequenced by incrementing the CAR through the rest of its microinstructions. 2. Next, the control memory must go through the routine that determines the effective address (EA) of the operands. The EA

Cont
computation routine in control memory can be reached through a branch microinstruction, which is conditioned on the status of the mode bits of the instruction. On the completion of the EA computation routine, the address of the operand is available in the MAR. Next step is the generation of the microoperations that execute the instruction fetched from the memory. The microoperation steps to be generated in processor registers depend on the operation code part of the instruction. The transformation from the instruction code bits to an address in control memory where the routine is located is referred to as a mapping process. When the execution of the instruction is completed, control must return to the fetch routine. This is accomplished by executing an unconditional branch microinstruction to the first address of the fetch routine.

3.

4.

ADDRESS SEQUENCING
Instruction code Mapping
logic

Status bits

Branch logic

MUX select

Multiplexers Subroutine register (SBR) Incrementer

Control address register

(CAR)

Control memory (ROM) select a status bit Branch address Microoperations

Sequencing Capabilities Required in a Control Storage

- Incrementing of the control address register - Unconditional and conditional branches - A mapping process from the bits of the machine instruction to an address for control memory - A facility for subroutine call and return

Conditional Branching
The branch logic provides decision making capabilities in the control unit. The status conditions are special bits in the system that provide parameter information such as the carry-out of an adder, the sign bit of a number, the mode bits of an instruction, and input or output status conditions. Information in the status bits can be nested and actions initiated based on their condition: whether their value is 0 or 1. The status bits, together with the field in the microinstruction that specifies a branch address, control the conditional branch decisions generated in the branch logic.

Conditional Branch
If Condition is true, then Branch (address from the next address field of the current microinstruction) else Fall Through Conditions to Test: O(overflow), N(negative), Z(zero), C(carry), etc.

CONDITIONAL BRANCHING
Load address

Control address register

Increment

MUX

Control memory

...
Status bits (condition) Condition select Next address Micro-operations

Unconditional Branch
Fixing the value of one status bit at the input of the multiplexer to 1

Mapping of instruction
Assume a computer with a simple instruction format has an operation code of 4 bits which can specify up to 16 distinct instructions. Assume further that the control memory has 128 words, requiring an address of 7 bits. For each operation code there exists a microprogram routine in control memory that executes the instruction. One simple mapping process that converts the 4-bit operation code to a 7-bit address for control memory consists of placing a 0 in the MSB of the address, transferring the 4 operation code bits, and clearing the two LSBs of the CAR. This provides for each computer instruction a microprogram routine with a capacity of 4 microinstructions. If the routine needs more than 4 microinstructions, it can use addresses 1000000 through 1111111. if it uses fewer than 4 microinstructions, the unused memory locations would be available for other routines.

Cont
A more general mapping rule can be formed by using a ROM to specify the mapping function. The bits of the instruction specify the address of a mapping ROM. The contents of the mapping ROM give the bits for the CAR. Thus, the microprogram routine that executes the instruction can be placed in any desired location in control memory. This mapping concept provides flexibility for adding instructions for control memory as the need arises.

MAPPING OF INSTRUCTIONS
Direct Mapping
OP-codes of Instructions ADD 0000 AND 0001 LDA 0010 STA 0011 BUN 0100 Mapping Bits
10 xxxx 010 Address 0000 0001 0010 0011 0100 ADD Routine AND Routine LDA Routine STA Routine BUN Routine Control Storage

. . .

Address 10 0000 010 10 0001 010 10 0010 010 10 0011 010 10 0100 010

ADD Routine AND Routine LDA Routine STA Routine BUN Routine

MAPPING OF INSTRUCTIONS TO MICROROUTINES

Mapping from the OP-code of an instruction to the address of the Microinstruction which is the starting microinstruction of its execution microprogram Machine Instruction Mapping bits Microinstruction address OP-code 1 0 1 1

Address

0 x x x x 0 0
0 1 0 1 1 0 0

Mapping function implemented by ROM or PLA OP-code Mapping memory (ROM or PLA)

Control address register Control Memory

MICROPROGRAM
Computer Configuration
MUX
10 AR Address 10 PC 0 Memory 2048 x 16 0

EXAMPLE

MUX 6 SBR 0 6 CAR 0 15 DR 0

Control memory 128 x 20 Control unit

Arithmetic logic and shift unit 15 AC 0

MACHINE INSTRUCTION FORMAT

Machine instruction format
15 14 11 10 Opcode I 0 Address

Sample machine instructions

Symbol ADD BRANCH STORE EXCHANGE OP-code 0000 0001 0010 0011 Description AC AC + M[EA] if (AC < 0) then (PC EA) M[EA] AC AC M[EA], M[EA] AC EA is the effective address

Microinstruction Format
3 F1 3 F2 3 F3 2 CD 2 BR 7 AD

F1, F2, F3: Microoperation fields CD: Condition for branching BR: Branch field AD: Address field

MICROINSTRUCTION FIELD DESCRIPTIONS - F1,F2,F3

F1 000 001 010 011 100 101 110 111 Microoperation None AC AC + DR AC 0 AC AC + 1 AC DR AR DR(0-10) AR PC M[AR] DR Symbol NOP ADD CLRAC INCAC DRTAC DRTAR PCTAR WRITE F2 000 001 010 011 100 101 110 111 Microoperation None AC AC - DR AC AC DR AC AC DR DR M[AR] DR AC DR DR + 1 DR(0-10) PC Symbol NOP SUB OR AND READ ACTDR INCDR PCTDR

F3 000 001 010 011 100 101 110 111

Microoperation None AC AC DR AC AC AC shl AC AC shr AC PC PC + 1 PC AR Reserved

Symbol NOP XOR COM SHL SHR INCPC ARTPC

MICROINSTRUCTION FIELD DESCRIPTIONS CD, BR

CD 00 01 10 11 Condition Always = 1 DR(15) AC(15) AC = 0 Symbol U I S Z Comments Unconditional branch Indirect address bit Sign bit of AC Zero value in AC

BR 00 01 10 11

Symbol JMP CALL RET MAP

Function CAR AD if condition = 1 CAR CAR + 1 if condition = 0 CAR AD, SBR CAR + 1 if condition = 1 CAR CAR + 1 if condition = 0 CAR SBR (Return from subroutine) CAR(2-5) DR(11-14), CAR(0,1,6) 0

SYMBOLIC MICROINSTRUCTIONS
Symbols are used in microinstructions as in assembly language A symbolic microprogram can be translated into its binary equivalent by a microprogram assembler. Sample Format five fields: Label:

label; micro-ops; CD; BR; AD may be empty or may specify a symbolic address terminated with a colon

Micro-ops: consists of one, two, or three symbols separated by commas CD: one of {U, I, S, Z}, where U: Unconditional Branch I: Indirect address bit S: Sign of AC Z: Zero value in AC

BR: AD:

one of {JMP, CALL, RET, MAP} one of {Symbolic address, NEXT, empty}

SYMBOLIC MICROPROGRAM - FETCH ROUTINE

During FETCH, Read an instruction from memory and decode the instruction and update PC Sequence of microoperations in the fetch cycle:
AR PC DR M[AR], PC PC + 1 AR DR(0-10), CAR(2-5) DR(11-14), CAR(0,1,6) 0

Symbolic microprogram for the fetch cycle:

FETCH: ORG 64 PCTAR READ, INCPC DRTAR U JMP NEXT U JMP NEXT U MAP

Binary equivalents translated by an assembler

Binary address 1000000 1000001 1000010

F1 110 000 101

F2 000 100 000

F3 000 101 000

CD 00 00 00

BR 00 00 11

AD 1000001 1000010 0000000

SYMBOLIC MICROPROGRAM
Control Storage: 128 20-bit words The first 64 words: Routines for the 16 machine instructions The last 64 words: Used for other purpose (e.g., fetch routine and other subroutines) Mapping: OP-code XXXX into 0XXXX00, the first address for the 16 routines are 0(0 0000 00), 4(0 0001 00), 8, 12, 16, 20, ..., 60

Partial Symbolic Microprogram

Label
ADD:

Microops
ORG 0 NOP READ ADD ORG 4 NOP NOP NOP ARTPC ORG 8 NOP ACTDR WRITE ORG 12 NOP READ ACTDR, DRTAC WRITE ORG 64 PCTAR READ, INCPC DRTAR READ DRTAR

CD
I U U S U I U I U U I U U U U U U U U

BR
CALL JMP JMP JMP JMP CALL JMP CALL JMP JMP CALL JMP JMP JMP JMP JMP MAP JMP RET

AD
INDRCT NEXT FETCH OVER FETCH INDRCT FETCH INDRCT NEXT FETCH INDRCT NEXT NEXT FETCH NEXT NEXT NEXT

BRANCH: OVER:

STORE:

EXCHANGE:

FETCH: INDRCT:

BINARY MICROPROGRAM
Micro Routine ADD Address Decimal Binary 0 0000000 1 0000001 2 0000010 3 0000011 4 0000100 5 0000101 6 0000110 7 0000111 8 0001000 9 0001001 10 0001010 11 0001011 12 0001100 13 0001101 14 0001110 15 0001111 64 65 66 67 68 1000000 1000001 1000010 1000011 1000100 F1 000 000 001 000 000 000 000 000 000 000 111 000 000 001 100 111 110 000 101 000 101 Binary Microinstruction F2 F3 CD 000 000 01 100 000 00 000 000 00 000 000 00 000 000 10 000 000 00 000 000 01 000 110 00 000 000 01 101 000 00 000 000 00 000 000 00 000 000 01 000 000 00 101 000 00 000 000 00 000 100 000 100 000 000 101 000 000 000 00 00 00 00 00 BR 01 00 00 00 00 00 01 00 01 00 00 00 01 00 00 00 00 00 11 00 10 AD 1000011 0000010 1000000 1000000 0000110 1000000 1000011 1000000 1000011 0001010 1000000 1000000 1000011 0001110 0001111 1000000 1000001 1000010 0000000 1000100 0000000

BRANCH

STORE

EXCHANGE

FETCH

INDRCT

This microprogram can be implemented using ROM

DESIGN OF CONTROL UNIT

- DECODING ALU CONTROL INFORMATION microoperation fields
F1 F2 F3

3 x 8 decoder 7 6 54 3 21 0

3 x 8 decoder 7 6 54 3 21 0

3 x 8 decoder 76 54 3 21 0

AND ADD DRTAC PCTAR DRTAR From From PC DR(0-10) 0 1 Multiplexers Arithmetic logic and shift unit

AC DR

Load

AC

Select

Load

AR

Clock

Implementation of Control Unit

COMPARISON OF CONTROL UNIT IMPLEMENTATIONS

Control Unit Implementation
Combinational Logic Circuits (Hard-wired)
Control Data Memory

IR

Status F/Fs

Control Unit's State Timing State Ins. Cycle State

Combinational Logic Circuits

Control Points

CPU

Microprogram
M e m o r y
Control Data IR Status F/Fs

Next Address Generation Logic

C S A R

Control Storage (-program memory)

C S D R

C P s

CPU

- NEXT MICROINSTRUCTION
External (MAP)

MICROPROGRAM SEQUENCER
Branch, CALL Address RETURN form Subroutine In-Line
L

ADDRESS LOGIC

S1S0 00 01 10 11

Address Source CAR + 1, In-Line SBR RETURN CS(AD), Branch or CALL MAP

Address source selection

3 2 1 0 S1 MUX1 S0

SBR

Subroutine CALL

Incrementer

Clock

CAR

Control Storage

MUX-1 selects an address from one of four sources and routes it into a CAR

- In-Line Sequencing CAR + 1 - Branch, Subroutine Call CS(AD) - Return from Subroutine Output of SBR - New Machine instruction MAP

MICROPROGRAM SEQUENCER
- CONDITION AND BRANCH CONTROL L BR field of CS
T Input I0 logic I
1

From I CPU S

1 MUX2 Select Z

Test

L(load SBR with PC) for subroutine Call S0 for next address S1 selection

CD Field of CS

Input Logic
I0I1T 000 001 010 011 10x 11x Meaning Source of Address In-Line JMP In-Line CALL RET MAP CAR+1 CS(AD) CAR+1 CS(AD) and SBR <- CAR+1 SBR DR(11-14) S1S0 00 10 00 10 01 11 L 0 0 0 1 0 0

S0 = I0 S1 = I0I1 + I0T L = I0I1T

MICROPROGRAM PROGRAMMED CONTROL

External (MAP)
L I Input I 0 logic 1 T 3 2 1 0 S1 MUX1 S0 SBR Load

1 I S Z

Incrementer
MUX2 Select Test Clock CAR

Control memory Microops CD BR AD

...

...

MICROINSTRUCTION FORMAT
Information in a Microinstruction - Control Information - Sequencing Information - Constant Information which is useful when feeding into the system These information needs to be organized in some way for - Efficient use of the microinstruction bits - Fast decoding Field Encoding - Encoding the microinstruction bits - Encoding slows down the execution speed due to the decoding delay - Encoding also reduces the flexibility due to the decoding hardware

HORIZONTAL AND VERTICAL MICROINSTRUCTION FORMAT

Horizontal Microinstructions Each bit directly controls each micro-operation or each control point Horizontal implies a long microinstruction word Advantages: Can control a variety of components operating in parallel. --> Advantage of efficient hardware utilization Disadvantages: Control word bits are not fully utilized --> CS becomes large --> Costly Vertical Microinstructions A microinstruction format that is not horizontal Vertical implies a short microinstruction word Encoded Microinstruction fields --> Needs decoding circuits for one or two levels of decoding
One-level decoding Field A 2 bits 2x4 Decoder 1 of 4 Field B 3 bits 3x8 Decoder 1 of 8 Two-level decoding Field A 2 bits 2x4 Decoder Field B 6 bits 6 x 64 Decoder Decoder and selection logic

NANOSTORAGE AND NANOINSTRUCTION

The decoder circuits in a vertical microprogram storage organization can be replaced by a ROM => Two levels of control storage First level - Control Storage Second level - Nano Storage Two-level microprogram
First level -Vertical format Microprogram Second level -Horizontal format Nanoprogram - Interprets the microinstruction fields, thus converts a vertical microinstruction format into a horizontal nanoinstruction format. Usually, the microprogram consists of a large number of short microinstructions, while the nanoprogram contains fewer words with longer nanoinstructions.

TWO-LEVEL MICROPROGRAMMING - EXAMPLE

* Microprogram: 2048 microinstructions of 200 bits each * With 1-Level Control Storage: 2048 x 200 = 409,600 bits * Assumption: 256 distinct microinstructions among 2048 * With 2-Level Control Storage: Nano Storage: 256 x 200 bits to store 256 distinct nanoinstructions Control storage: 2048 x 8 bits To address 256 nano storage locations 8 bits are needed * Total 1-Level control storage: 409,600 bits Total 2-Level control storage: 67,584 bits (256 x 200 + 2048 x 8)
Control address register 11 bits Control memory 2048 x 8 Microinstruction (8 bits) Nanomemory address Nanomemory 256 x 200 Nanoinstructions (200 bits)