CHAPTER 2

FET and MOSFET

 Field Effect Transistor (FET)
• In the Bipolar Junction Transistor (BJT), the output Collector current of the transistor is proportional to
input current flowing into the Base terminal of the device, thereby making the bipolar transistor a
“CURRENT” operated device as a smaller current can be used to switch a larger load current.
• The Field Effect Transistor, or simply FET however, uses the voltage that is applied to their input
terminal, called the Gate to control the current flowing through them resulting in the output current being
proportional to the input voltage. As their operation relies on an electric field (hence the name field effect)
generated by the input Gate voltage, this then makes the Field Effect Transistor a “VOLTAGE” operated
device.
• The Field Effect Transistor is a three terminal unipolar semiconductor device that has very similar
characteristics to those of their Bipolar Transistor .Because of high efficiency, instant operation, robust and
cheap nature, FET are used in most electronic circuit applications to replace their equivalent bipolar
junction transistors.
• Field effect transistors can be made much smaller than an equivalent BJT transistor and along with their
low power consumption and power dissipation makes them ideal for use in integrated circuits(IC’s).
• Similar to the types of bipolar transistor construction, such as NPN and PNP, FET’s are also classified into
two basic classifications, called as the N-channel FET and the P-channel FET.
• The path through which current flows between these terminals is called the “channel” which may be made
of either a P-type or an N-type semiconductor material.
• The control of current flowing in this channel is achieved by varying the voltage applied to the Gate. As
their name implies, Bipolar Transistors are “Bipolar” devices because they operate with both types of charge
carriers, Holes and Electrons. The Field Effect Transistor on the other hand is a “Unipolar” device that
depends only on the conduction of electrons (N-channel) or holes (P-channel).
• The Field Effect Transistor has one major advantage over its standard bipolar transistor is that their input
impedance ( Rin ) is very high,while the BJT is comparatively low. This very high input impedance makes
them very sensitive to input voltage signals, but the price of this high sensitivity also means that they can be
easily damaged by static electricity.
• There are two main types of field effect transistor, the Junction Field Effect Transistor or JFET and
the Insulated-gate Field Effect Transistor or IGFET), which is more commonly known as the
standard Metal Oxide Semiconductor Field Effect Transistor or MOSFET for short.
• Junction Field Effect Transistor (JFET)
• A junction field effect transistor is a voltage controlled device i.e. the output characteristics of the device are
controlled by input voltage. JFET has three terminals Gate, Drain, and Source.
• JFET are used as voltage controlled resistors or as a switch, or even make an amplifier using the JFET. It is
also an energy efficient version to replace the BJTs. JFET provides low power consumption and fairly low
power dissipations, thus improving the overall efficiency of the circuit.
• A JFET is a three terminal semiconductor device in which current conduction is by one type of carrier i.e.
electrons or holes.
• The current conduction is controlled by means of an electric field between the gate and the conducting channel
of the device.
• The JFET has high input impedance and low noise level.
• JFET Construction
• A JFET consists of a p-type or n-type silicon bar containing two pn junctions at the sides as shown in fig

• The bar forms the conducting channel for the charge carriers.
• If the bar is of p-type, it is called p-channel JFET as shown in fig.1(i) and if the bar is of n-type, it is called n-
channel JFET as shown in fig.1(ii). The two pn junctions forming diodes are connected internally and a
common terminal called gate is taken out.
• Other terminals are source and drain taken out from the bar. Thus a JFET has three terminals such as , gate (G),
source (S) and drain (D).
• Fig.2 (i) shows the n-channel JFET polarities and fig.2 (ii) shows the p-channel JFET polarities.

Fig.2 (i) Fig.2 (ii)

• In each case, the voltage between the gate and source is such that the gate is reverse biased.
• The source and the drain terminals are interchangeable.
The following points should be noted:
• The input circuit ( i.e. gate to source) of a JFET is reverse biased. This means that the device has high input
impedance.
• The drain is so biased w.r.t. source that drain current I D flows from the source to drain.
• In all JFETs, source current IS is equal to the drain current i.e IS = ID.
 Principle and Working of JFET
• Principle of JFET
• The two pn junctions at the sides form two depletion layers.
• The current conduction by charge carriers (i.e. electrons) is through the channel between the two depletion
layers. The width and hence resistance of this channel can be controlled by changing the input voltage V GS.
• The greater the reverse voltage VGS, the wider will be the depletion layer and narrower will be the
conducting channel. The narrower channel means source to drain current decreases with increase in the
resistance.
• Reverse will happen when VGS decreases.
• Thus JFET operates on the principle that width and hence resistance of the conducting channel can be varied
by changing the reverse voltage VGS.
• In other word, the magnitude of drain current ID can be changed by altering VGS.
• Working of JEFT
• The working of JFET can be explained as follows:
Case-i:
• When a voltage VDS is applied between drain and source terminals and voltage on the gate is zero as shown
in fig.3(i), the two pn junctions at the sides of the bar establish depletion layers.
• The electrons will flow from source to drain through a channel between the depletion layers.
• The size of the depletion layers determines the width of the channel and hence current conduction through
the bar.

.
Case-ii:
When a reverse voltage VGS is applied between gate and source terminals, as shown in fig.3(ii), the width of
depletion layer is increased.
• This reduces the width of conducting channel, thereby increasing the resistance of n-type bar.
• Consequently, the current from source to drain is decreased.
• On the other hand, when the reverse bias on the gate is decreased, the width of the depletion layer also
decreases.
• This increases the width of the conducting channel and hence source to drain current.
• A p-channel JFET operates in the same manner as an n-channel JFET except that channel current carriers will
be the holes instead of electrons and polarities of VGS and VDS are reversed.
• Schematic Symbol of JFET

• Advantages of JFET
• A JFET is a voltage controlled, constant current device in which variation in input voltage control the output
current. Some of the advantages of JFET are:
• It has a very high input impedance. This permits high degree of isolation between the input and output
circuits.
• A JFET has a negative temperature co-efficient of resistance. This avoids the risk of thermal runaway.
• A JFET has a very high power gain.
• A JFET has a smaller size, longer life and high efficiency.
• Difference Between JFET and BJT
• The JFET differs from an ordinary BJT in the following ways:
• In a JFET, there is only one type of carrier,i.e. holes in p-type channel and electrons in n-type channel.
For this reason it is also called unipolar transistor.However, in an ordinary BJT, both electrons and holes
play role in conduction. Therefore, it is called as bipolar transistor.
• As the input circuit of a JFET is reverse biased, therefore, it has a high input impedance. However, the
input circuit of a BJT is forward biased and hence has low input impedance.
• The primary functional difference between the JFET and BJT is that no current enters the gate of
JFET. However, in typical BJT base current might be a few µA.
• A BJT uses the current into its base to control a large current between collector and emitter. Whereas a
JFET uses voltage on the gate terminal to control the current between drain and source.
• In JFET, there is no junction. Therefore, noise level in JFET is very small.
 Characteristics of JFET
• The characteristics of JFET is defined by a plotting a curve between the drain current and drain-source
voltage. The variation of drain current with respect to the voltage applied at drain-source terminals keeping
the gate-source voltage constant is termed as its characteristics.
• Basically, the characteristics are of two types that are output characteristics or drain characteristics, and the
another is transfer characteristics.
• In the first case the output characteristics are observed when there is no bias, i.e. there is no voltage applied
between gate and source terminals. Another condition is that the biasing is applied between gate and source
terminals. In both the condition the variation of drain current is different.
• Output Characteristics or Drain Characteristics
(1) In the absence of external bias: In this case, as there is no voltage between gate and source terminal, thus,
the drain current will flow from drain terminal to source terminal. We have already discussed in the working
of JFET that majority charge carriers flow from source to drain and as a consequence of which the current
flows from drain to source.
• The channel width is more as the width of depletion layer will not vary initially because there is no external
reverse biasing. This allows a large magnitude of current to flow through the channel. In this case, the N-type
channel will simply behave as resistance region. The flow of current from drain to source will create the
voltage drop between gate and source. This will eventually result in reverse biasing of the gate-source
terminal.
• The characteristics curves shows the three different regions of operation for a JFET and these are given as:
• Channel Ohmic Region: The region to the left of the knee point in the characteristics curve is the channel
ohmic region. When VGS = 0 the depletion layer of the channel is very small and the JFET acts like a voltage
controlled resistor. Thus drain current Id increases linearly with Vds in ohmic region.
• Pinch-off region or saturation region: The region in the curve above which the drain current does not
increases further no matter how much we are increasing the drain to source voltage, this point is termed as the
pinch-off point.
• Breakdown Region – The voltage between the Drain and the Source, ( VDS ) is high enough to causes the
JFET’s resistive channel to break down and pass uncontrolled maximum current.
• Terminologies involved in JFET characteristics
• Knee Point: There exists a point in the characteristics curve where the variation of drain current with drain-
source voltage appears to be linear. But after this point, the linearity changes into a curve.
• Pinch-off Voltage: The voltage at the pinch-off point is termed as pinch-off voltage because at this voltage
the current is completely turned to be constant.
• Drain-Source Saturation Current: The drain to source saturation current is the current which becomes
constant or completely enters a saturation state.
(2) With external bias: When the external bias is applied to the gate-source terminal, the gate-source terminal
becomes reversed bias externally. Obviously, if we are supplying an external voltage, then we can achieve the
pinch-off point quite early as compared to the circuit which is not biased.
• It is clearly evident from the characteristics curve of external bias, the different values of voltage give
different values of current.
• When we are observing the drain characteristics with respect to the variation in drain-source voltage, then the
value of gate-source voltage should be kept constant.
Transfer Characteristics
• The transfer characteristics can be determined by observing different values of drain current with variation in
gate-source voltage provided that the drain-source voltage should be constant. The transfer characteristics are
just opposite to drain characteristics.
• One just needs to remember the concept that in drain characteristics we are keeping the gate-source voltage
constant and determining the values of drain current at different values of drain-source voltage while in
transfer characteristics we are keeping the value of drain-source voltage constant. The characteristic curve of
transfer characteristics of JFET is described below; it can be easily observed that the value of drain current
varies inversely with respect to gate-source voltage when the drain-source voltage is constant.
• The output characteristics or drain characteristics and transfer characteristics of an N-channel JFET is
explained. The characteristics curve of P-channel will remain same. The only difference which will occur is
that in case of P-channel the current contributing carriers will be hole rather than electrons in N-channel.
Besides, the polarities of gate-source voltage and drain-source voltage will also be reversed in case of P-
channel JFET.
• For normal operation, VGS is biased to be somewhere between VP and 0. The Drain current becomes zero
when VGS = VP. Then we can calculate the Drain current, ID for any given bias point in the saturation or active
region as follows:
• Drain current in the active region is given by,

• The parameters of JFET Characteristics are:

(i) Drain Resistance(Rd):- It is the ratio of change in output drain-source voltage to output drain current.

(ii) Transconductance (gm ):- It is the ratio of change in output drain-current to input gate source voltage.
gm = ID /VGS
(iii) Amplification factor(µ):- It is the ratio of change in output drain-source voltage VDS to input gate-source voltage
VGS
µ= VDS /VGS
It is also defined as product of drain resistance (Rd) and transconductance (gm)
µ= (Rd) x (gm)

FET biasing circuits

As transfer characteristics of FET is non-linear, it is difficult to obtain the operating point. So to obtain the correct
operating point of the circuit, the biasing of FET is required. There are three types of FET biasing circuits:-
1. Fixed bias circuits
2. Self bias circuits
3. Voltage bias circuits

The general relationships that can be applied to the dc analysis of all FET amplifiers are
IG = 0 and ID = IS
For JFETs and depletion-type MOSFETs, Shockley’s equation is applied to relate the input and output quantities
• For enhancement-type MOSFETs, the following equation is applicable
ID = k(VG –VT)²

(A) FIXED-BIAS CONFIGURATION

(A) FIXED-BIAS CONFIGURATION

Vi &Vo:input & output ac levels C1&C2: the coupling capacitors (open for dc analysis & low impedance (essentially
short circuit) for ac analysis .
• As reverse voltage is applied to gate of FET, it offers very high impedance. The gate current IG flowing through the circuit is zero. Thus
voltage drop across RG is zero. i.e VRG = IG RG = 0. Thus it acts as the short circuit.
• Fixed dc bias is obtained using a battery VQG. This battery ensures that the gate is always negative with respect to source and no current
flows through resistor RG and gate terminal that is IG =0.
• Thus the fixed battery provides a voltage VGS to bias the N-channel JFET, Hence it is called as fixed biasing configuration.
• Calculation of VGS
• For DC analysis IG =0., applying KVL to the input circuits
VGS+ VGG=0
Therefore, VGS= - VGG
As VGS is a fixed dc supply, hence the name fixed bias circuit
• Calculate IDQ
IDQ=IDss(1- VGS/VGp)2
substituting the value of VGS from above equation , IDQ=IDss(1 + VGG/VGp)2
• Calculate VDS
• This current IDQ then causes a voltage drop across the drain resistor R D and is given as
VDSQ = VDD – ID RD
• On the other hand, graphical analysis would require a plot of Shockley’s equation. Thus we choose that
VGS=VP/2 which results in a drain current of IDSS/4 when plotting the curve

• Disadvantage
• The fixed bias circuit of FET requires two power supplies.
• (B) Self-Bias circuits
• Self-Bias circuits is the most common method for biasing a JFET. The self-bias configuration eliminates the need
for two dc supplies as required for fixed-bias configuration. The controlling gate-to-source voltage, VGS is now
determined by the voltage across the resistance Rs introduced in the circuit. Self-bias circuit for N-channel JFET is
shown in figure

For the dc analysis, the capacitors can again be replaced by “open circuits” and the resistor RG replaced by short
circuit equivalent since IG = 0A. The gate source junction of JFET must be always in reverse biased condition .No
gate current flows through the reverse-biased gate-source, the gate current I G = 0 and, therefore, vG = iG RG = 0
The current through Rs is the source current IS, but IS = ID and
V s= I SR s = I D R s
• The gate-source voltage is then
VGS = VG - Vs = 0 – ID RS = – ID RS
• So voltage drop across resistance Rs provides the biasing voltage VGg and no external source is required for biasing and
this is the reason that it is called self-biasing.
• 2)Calculate IDQ
ID=IDSS(1- VGS/ VP)2
• Substituting the value of VGS
ID= IDSS (1+IDRS / VP)2
• 3)Calculate vDs
• The operating point (that is zero signal ID and VDS) can easily be determined from equation given below :
VDS = VDD – ID(RD + RS)
Self biasing of a JFET stabilizes its quiescent operating point against any change in its parameters like transconductance.
Any increase in voltage drop across RS, therefore, gate-source voltage, VGS becomes more negative and thus increase in
drain current is reduced.
(C) Voltage -Divider Bias circuits
The resistors RGl and RG2 form a potential divider across drain supply V DD. The voltage V2 across RG2 provides the
necessary bias. The additional gate resistor R Gl from gate to supply voltage facilitates in larger adjustment of the dc bias
point and permits use of larger valued RS.
• The coupling capacitors are assumed to be open circuit for DC analysis

• Let current flowing through RGl and RG2 are I1 and I2 and current at gate terminal is IG. Then by applying KCL to the
input loop we get,
I1 = I2 + IG but as input junction is reverse biased, it offers very high impedance causing I G zero. Therefore, I1 = I2
= I. Thus total current, I = VDD / RGl + RG2 . Thus voltage drop across RG2 is given by.
VG =V2 = (VDD/R G1 + R G2 ) *RG2
Applying KVL to the input circuit we get
VGS= VG – VS
= V G - I D RS
• From above equation,
ID = (-1/R S ) VGS + VG /R S
Comparing the above equation with line equation, y = mx + c, we say that y = ID, x = VGS and m = -1/R S which is slope of line. To
calculate co-ordinates of operating point,,
I) we consider x co-ordinate i.e VGS = 0 in above equation. So we obtain
ID = VG /R S
II) we consider y co-ordinate i.e ID = 0. Hence we get
VGS = VG

If the value of R S is increased, the slope of line(m) will decrease and will shift towards x-axis and if the value of R S is decreased, the slope
of line will increase and will shift towards Y-axis.
• Applying KVL to the output circuit we get
VDS = VDD – ID (RD + RS)
• The operating point of a JFET amplifier using the Voltage -Divider Bias is determined by
IDQ= IDSS(1- VGS/ VP)2
VDSQ = VDD – ID (RD + RS)
VGSQ = VG – ID RS
FET Equivalent Circuit
FET small signal equivalent circuit is drawn by considering transconductance and drain resistance .
The output drain current ID is expressed in terms of input transconductance (gm ) and output drain resistance RD
As gm = ID /VGS and RD= VDS / ID, we can write equation for ID considering the two equations.
So ID is expressed as, ID =gm VGS + VDS/ RD
• The complete FET Equivalent Circuit Model is shown in Fig. 11-5(a). It is seen that tilt source terminal is common
to both input and out, so this is a common-source equivalent circuit. Resistor R GS between the gate and source
terminals is the resistance of the reverse-biased gate-source junction, and C gs is the junction capacitance. So, a
signal applied to the input sees RGS in parallel with Cgs.
• The output stage of the FET Equivalent Circuit Model is represented as a current source (Y fs vgs) supplying current
to the drain resistance (rd). Yfs is the forward transfer admittance for the FET, and vgs is the ac signal voltage
developed across the gate-source terminals, so the ac drain current is (Yfs vgs). The drain-source capacitance (Cds)
appears in parallel with rd, and the gate-drain capacitance (Cgd) is shown connected between the input and output
stages. Admittance Yfs is same as Transconductance gm.
• For low- and medium-frequency operations the capacitances can be neglected, and the equivalent circuit is then as
shown in Fig. 11-5(b). This is the FET model (or equivalent circuit) normally used in ac circuit analysis.
• MOSFET
• FETs have a few disadvantages like high drain resistance, moderate input impedance and slower operation. To overcome these
disadvantages, the MOSFET which is an advanced FET is invented.
• In case of JFET, the gate must be reverse biased for proper operation of the device i.e. it can only have negative gate operation
for n-channel and positive gate operation for p-channel. That means we can only decrease the width of the channel from its
zero-bias size. This type of operation is known as depletion-mode operation. Therefore, a JFET can only be operated in the
depletion mode. However, there is a field effect transistor that can be operated to enhance the width of the channel i.e. it can
have enhancement-mode operation. Such a FET is called MOSFET.
• MOSFET stands for Metal Oxide Semiconductor Field Effect Transistor. This is also called as IGFET meaning Insulated
Gate Field Effect Transistor. The FET is operated in both depletion and enhancement modes of operation.
• Classification of MOSFETs
• Depending upon the type of materials used in the construction, and the type of operation, the MOSFETs are classified as
in the following figure.

• The N-channel MOSFETs are simply called as NMOS. The symbols for N-channel MOSFET are as given below.

The P-channel MOSFETs are simply called as PMOS. The symbols for P-channel MOSFET are as given below.
• Construction of N- Channel Enhancement MOSFET
• The MOSFET which is formed in which the conduction is due to the majority charge carriers called electrons
is defined as N-channel MOSFET. When this MOSFET is activated as ON this condition results in the
maximum amount of the current flow through the device.
• A lightly doped P-type substrate is taken into which two heavily doped N-type regions are diffused, which act
as source and drain. Between these two N+ regions, there occurs diffusion to form an N channel, connecting
drain and source.

• A thin layer of Silicon dioxide (SiO2) is grown over the entire surface and holes are made to draw ohmic
contacts for drain and source terminals. The substrate is connected to the source or ground terminals.
• Working of N-Channel Enhancement MOSFET
• In N Channel Enhancement MOSFET a lightly doped p-type substrate forms the body of the device and source and drain regions
are heavily doped with n-type impurities

• When VGS= 0V, here is no channel connecting source and drain.

• The p-substrate has only a few thermally produced free electrons(minority carriers) so that drain current is almost zero. For this
reason, E-MOSFET is normally OFF when VGS = 0V.
• Now, we apply a positive voltage to the gate terminal. Due to positivity of the gate, free electrons i.e. minority carriers of the p-
type substrate get attracted towards the gate and form a layer of negative ions just below the dielectric layer by recombining these
free electrons with holes.
• Thus the E-MOSFET is turned ON and drain current ID starts flowing from the source to the drain.
• The minimum value of VGS that turns the E-MOSFET ON is called threshold voltage[VGS(th)].
• When VGS is less than VGS(th), there is no induced channel and the drain current IDis zero.
• When VGS is equal to VGS(th), the E-MOSFET is turned ON and the induced channel conducts drain current
from the source to the drain.
• If we continually increase the positive gate voltage, after the threshold voltage level, the recombinations
process gets saturated and then free electrons start to accumulate at the place to form a conductive channel of
free electrons.
• The resistance of the channel depends on the number of free electrons in the channel and the number of free
electrons in the channel again depends on the gate potential of the device.
• As the concentration of free electrons forms the channel, and the current through the channel gets enhanced
due to increase in gate voltage, we name the MOSFET as N – Channel Enhancement MOSFET.
(2) N-Channel Depletion MOSFET
• The construction is similar to the enhancement MOSFET but the working is different in comparison to it. In
a depletion type or DE-MOS, a channel for conduction is already constructed physically. Due to this, current
flows in between the source and drain without any gate bias voltage.
• The channel conducts even when VGS = 0.
• DE-MOSFET has the ability to work at both positive and negative gate potential.
• In a DE-MOSFET when the gate potential is made negative with respect to the substrate, it causes repulsion
of negative charge carriers out of the initially formed channel. This increases the channel resistance which
resultantly reduces the drain current.
• Thus by changing the gate voltage, the output drain current can be controlled.
• As reverse voltage is applied, the width of the depletion region increases and channel width is reduced thus
reducing the drain current. Hence it is termed as depletion MOSFET.

The working of P-type enhancement and depletion mosfet is same as that of N-type MOSFET but only
difference is conduction is due to novement of holes.
 MOSFET characteristics
• MOSFETs are tri-terminal, unipolar, voltage-controlled, high input impedance devices which form an
integral part of vast variety of electronic circuits.
• These devices can be classified into two types viz., depletion-type and enhancement-type
• MOSFETs are tri-terminal, unipolar, voltage-controlled, high input impedance devices which form an
integral part of vast variety of electronic circuits.
• These devices can be classified into two types viz., depletion-type and enhancement-type
• Any MOSFET is seen to exhibit three operating regions viz.,
1) Cut-Off Region
Cut-off region is a region in which the MOSFET will be OFF as there will be no current flow through it. In
this region, MOSFET behaves like an open switch and is thus used when they are required to function as
electronic switches.
2) Ohmic or Linear Region
Ohmic or linear region is a region where in the current I DS increases with an
3) Saturation Region
In saturation region, the MOSFETs have their IDS constant inspite of an increase in VDS and occurs once
VDS exceeds the value of pinch-off voltage VP. Under this condition, the device will act like a closed switch
through which a saturated value of IDS flows.
• Let us now analyze the biasing conditions at which these regions are experienced for each kind of MOSFET.
• n-channel Enhancement-type MOSFET
• Figure 1a shows the transfer characteristics (drain-to-source current I DS versus gate-to-source voltage VGS) of
n-channel Enhancement-type MOSFETs. From this, it is evident that the current through the device will be
zero until the VGS exceeds the value of threshold voltage VT.
• This is because under this state, there is no channel which will be connecting the drain and the source
terminals.
• Under this condition, even an increase in VDS will result in no current flow as indicated by the corresponding
output characteristics (IDS versus VDS) shown by Figure 1b. As a result this state represents nothing but the cut-
off region of MOSFET’s operation. Next, once VGS crosses VT, the current through the device increases with
an increase in IDS initially (Ohmic region) and then saturates to a value as determined by the V GS (saturation
region of operation) i.e. as VGS increases, even the saturation current flowing through the device also
increases.
• This is evident by Figure 1b where IDSS2 is greater than IDSS1 as VGS2 > VGS1, IDSS3 is greater than IDSS2 as VGS3 > VGS2, so on and so
forth. Further, Figure 1b also shows the locus of pinch-off voltage (black discontinuous curve), from which V P is seen to
increase with an increase in VGS.
• p-channel Enhancement-type MOSFET
• Figure 2a shows the transfer characteristics of p-type enhancement MOSFETs from which it is evident that IDS remains zero
(cutoff state) untill VGS becomes equal to -VT.
• This is because, only then the channel will be formed to connect the drain terminal of the device with its source terminal. After
this, the IDS is seen to increase in reverse direction (meaning an increase in ISD, signifying an increase in the device current
which will flow from source to drain) with the decrease in the value of VDS.

• This means that the device is functioning in its ohmic region wherein the current through the device increases with an increase
in the applied voltage (which will be VSD).
• However as VDS becomes equal to –VP, the device enters into saturation during which a saturated amount of
current (IDSS) flows through the device, as decided by the value of V GS.
• Further it is to be noted that the value of saturation current flowing through the device is seen to increase as
the VGS becomes more and more negative i.e. saturation current for V GS3 is greater than that for VGS2 and that
in the case of VGS4 is much greater than both of them as VGS3 is more negative than VGS2 while VGS4 is much
more negative when compared to either of them (Figure 2b).
• In addition, from the locus of the pinch-off voltage it is also clear that as V GS becomes more and more
negative, even the negativity of VP also increases.
• n-channel Depletion-type MOSFET
• The transfer characteristics of n-channel depletion MOSFET shown by Figure 3a indicate that the device
has a current flowing through it even when VGS is 0V. This indicates that these devices conduct even when
the gate terminal is left unbiased, which is further emphasized by the V GS0 curve of Figure 3b.
• Under this condition, the current through the MOSFET is seen to increase with an increase in the value of V DS
(Ohmic region) untill VDS becomes equal to pinch-off voltage VP. After this, IDS will get saturated to a particular
level IDSS (saturation region of operation) which increases with an increase in V GS i.e. IDSS3 > IDSS2 > IDSS1, as VGS3 >
VGS2 > VGS1.
• Further, the locus of the pinch-off voltage also shows that VP increases with an increase in VGS.
• However it is to be noted that, if one needs to operate these devices in cut-off state, then it is required to make V GS
negative and once it becomes equal to -VT, the conduction through the device stops (IDS = 0)
• p-channel Depletion-type MOSFET
• The transfer characteristics of p-channel depletion mode MOSFETs (Figure 4a) show that these devices will be
normally ON, and thus conduct even in the absence of VGS.
• This is because they are characterized by the presence of a channel in their default state due to which they have
non-zero IDS for VGS = 0V, as indicated by the VGS0 curve of Figure 4b. Although the value of such a current
increases with an increase in VDS initially (ohmic region of operation), it is seen to saturate once the V DS exceeds
VP (saturation region of operation).
• The value of this saturation current is determined by the VGS, and is seen to increase in negative direction as VGS
becomes more and more negative.
• For example, the saturation current for VGS3 is greater than that for VGS2 which is however greater when compared
to that for VGS1. This is because VGS2 is more negative when compared to VGS1, and VGS3 is much more negative
when compared to either of them.
• Next, one can also note from the locus of pinch-off point that even V P starts to become more and more
negative as the negativity associated with the VGS increases.
• Lastly, it is evident from Figure 4a that inorder to switch these devices OFF, one needs to increase V GS such
that it becomes equal to or greater than that of the threshold voltage V T.
 MOSFET As A Switch
• MOSFETs exhibit three regions of operation viz., Cut-off, Linear or Ohmic and Saturation. Among these,
when MOSFETs are to be used as amplifiers, they are required to be operated in their ohmic region wherein
the current through the device increases with an increase in the applied voltage.
• On the other hand, when the MOSFETs are required to function as switches, they should be biased in such a
way that they alter between cut-off and saturation states. This is because, in cut-off region, there is no current
flow through the device while in saturation region there will be a constant amount of current flowing through
the device, just relating the behavior of an open and closed switch, respectively.
• Figure 1 shows a simple circuit which uses an n-channel enhancement MOSFET as a switch. Here the drain
terminal (D) of the MOSFET is connected to the supply voltage VS via the drain resistor RD while its source
terminal (S) is grounded. Further, it has an input voltage Vi applied at its gate terminal (G) while the output
Vo is drawn from its drain.
• Now consider the case where Vi applied is 0V, which means the gate terminal of the MOSFETis left unbiased. As a result,
the MOSFET will be OFF and operates in its cutoff region wherein it offers a high impedance path to the flow of current
which makes the IDS almost equivalent to zero. As a result, even the voltage drop across RD will become zero due to which
the output voltage Vo will become almost equal to VS.
• Next, consider the case where the input voltage V i applied is greater than the threshold voltage V T of the device. Under
this condition, the MOSFET will start to conduct and if the V S provided is greater than the pinch-off voltage V P of the
device (usually it will be so), then the MOSFET starts to operate in its saturation region. This further means that the device
will offer low resistance path for the flow of constant IDS, almost acting like a short circuit. As a result, the output voltage
will be pulled towards low voltage level, which will be ideally zero.
• it is evident that the output voltage alters between VS and zero depending on whether the input provided is less than or
greater than VT, respectively. Thus, it can be concluded that MOSFETs can be made to function as electronic switches
when made to operate between cut-off and saturation operating regions.
• Similar to the case of n-channel enhancement type MOSFET, even n-channel depletion type MOSFETs can be used to
perform switching action as shown by Figure 2. The behaviour of such a circuit is seen to be almost identical to that
explained above except the fact that for cut-off, the gate voltage V G needs to be made negative and should be lesser than
-VT.
• Next, Figure 3 shows the case wherein the p-channel enhancement MOSFET is used as a switch. Here it is seen that
the supply voltage VS is applied at its source terminal (S) and the gate terminal is provided with the input voltage V i
while the drain terminal is grounded via the resistor RD. Further the output of the circuit V o is obtained across RD,
from the drain terminal of the MOSFET .
• In the case of p-type devices the conduction current will be due to holes and will thus flow from source to drain I SD,
and not from drain to source (IDS) as in the case of n-type devices. Now, let us assume that the input voltage which is
nothing but the gate voltage VG of the MOSFET goes low. This causes the MOSFET to switch ON and to offer a low
(almost negligible) resistance path to the current flow. As a result heavy current flows through the device which
results in a large voltage drop across the resistor RD. This inturn results in the output which is almost equal to the
supply voltage VS.

• Next, consider the case where Vi goes high i.e. when Vi will be greater than the threshold voltage of the device (V T
will be negative for these devices). Under this condition, the MOSFET will be OFF and offers a high impedance path
for the current flow. This results in almost zero current leading to almost zero voltage at the output terminal.
• Similar to this, even p-channel depletion-type MOSFETs can be used to perform switching action as shown by
Figure 4. The working of this circuit is almost similar to the one explained above except for the fact that here
the cut-off region is experienced only if Vi = VG is made positive such that it exceeds the threshold voltage of
the device.

• The table presented below summarizes the discussion presented above.

 CMOS- Complementary MOS
• CMOS Working Principle and Applications
• The term CMOS stands for “Complementary Metal Oxide Semiconductor”. CMOS technology is one of the
most popular technology in the computer chip design industry and broadly used today to form integrated
circuits in numerous and varied applications. Today’s computer memories, CPUs and cell phones make use
of this technology due to several key advantages. This technology makes use of both P channel and N
channel semiconductor devices. One of the most popular MOSFET technologies available today is the
Complementary MOS or CMOS technology.
• CMOS (Complementary Metal Oxide Semiconductor)
• The main advantage of CMOS over NMOS and BIPOLAR technology is the much smaller power
dissipation. Unlike NMOS or BIPOLAR circuits, a Complementary MOS circuit has almost no static power
dissipation. Power is only dissipated in case the circuit actually switches. This allows integrating more
CMOS gates on an IC than in NMOS or bipolar technology, resulting in much better performance.
Complementary Metal Oxide Semiconductor transistor consists of P-channel MOS (PMOS) and N-channel
MOS (NMOS).
• NMOS
• NMOS is built on a p-type substrate with n-type source and drain diffused on it. In NMOS, the majority
carriers are electrons. When a high voltage is applied to the gate, the NMOS will conduct. Similarly, when a
low voltage is applied to the gate, NMOS will not conduct. NMOS are considered to be faster than PMOS,
since the carriers in NMOS, which are electrons, travel twice as fast as the holes

• PMOS
• P- channel MOSFET consists P-type Source and Drain diffused on an N-type substrate. Majority carriers are
holes. When a high voltage is applied to the gate, the PMOS will not conduct. When a low voltage is applied
to the gate, the PMOS will conduct. The PMOS devices are more immune to noise than NMOS devices.
• CMOS Working Principle
• In CMOS technology, both N-type and P-type transistors are used to design logic functions. The same signal
which turns ON a transistor of one type is used to turn OFF a transistor of the other type.
• In CMOS logic gates a collection of n-type MOSFETs is arranged in a pull-down network between the output
and the low voltage power supply rail (Vss or quite often ground). Instead of the load resistor of NMOS logic
gates, CMOS logic gates have a collection of p-type MOSFETs in a pull-up network between the output and
the higher-voltage rail (often named Vdd). Thus, if both a p-type and n-type transistor have their gates
connected to the same input, the p type MOSFET will be ON when the n-type MOSFET is OFF, and vice-
versa. The networks are arranged such that one is ON and the other OFF for any input pattern as shown in the
figure below

• CMOS offers relatively high speed, low power dissipation, high noise margins in both states, and will operate
over a wide range of source and input voltages (provided the source voltage is fixed).
• CMOS Inverter
• The inverter circuit as shown in the figure below. It consists of PMOS and NMOS FET. The input Vin serves as the gate
voltage for both transistors.
• The NMOS transistor has input from Vss (ground) and the PMOS transistor has input from Vdd. The terminal Y is output.
When a high voltage (~ Vdd) is given at input terminal (A) of the inverter, the PMOS becomes an open circuit, and
NMOS switched ON so the output will be pulled down to Vss.
• When a low-level voltage (<Vdd, ~0v) applied to the inverter, the NMOS switched OFF and PMOS switched ON. So the
output becomes Vdd or the circuit is pulled up to Vdd.
• The tabular form of CMOS inverter I shown in fig
• Input Logic input Output Logic output
• 0V 0 Vdd 1
• Vdd 1 0 0
• CMOS NAND Gate
• The below figure shows a 2-input Complementary MOS NAND gate. It consists of two series NMOS transistors between
Y and Ground and two parallel PMOS transistors between Y and VDD.
• If either input A or B is logic 0, at least one of the NMOS transistors will be OFF, breaking the path from Z to Ground. But
at least one of the p MOS transistors will be ON, creating a path from Y to VDD.

• Hence, the output Y will be high. If both inputs are high, both of the nMOS transistors will be ON and both of the pMOS
transistors will be OFF. Hence, the output will be logic low.
• The Truth table of the NAND logic gate given in the below table
A B Pull-down Pull-up Output
network network Y
0 0 OFF ON 1
0 1 OFF ON 1
1 0 OFF ON 1
1 1 ON OFF 0

• CMOS NOR Gate

• A 2-input NOR gate is shown in the figure below. The NMOS transistors are in parallel to pull the output low
when either input is high. The PMOS transistors are in series to pull the output high when both inputs are low,
as given in the below table. The output is never left floating.
A B Pull-down network Pull-up network Output
Y

0 0 OFF ON 1
0 1 ON OFF 0
1 0 ON OFF 0
1 1 ON OFF 0

CMOS Applications Complementary MOS processes were widely implemented and have
fundamentally replaced NMOS and bipolar processes for nearly all digital logic applications. The CMOS
technology has been used for the following digital IC designs.
Computer memories, CPUs ,Microprocessor designs , Used to design application-specific integrated
circuits