Junction Field Effect Transistor

(JFET)
 Introduction (FET)

• Field-effect transistor (FET) are important devices such

as BJTs
• Also used as amplifier and logic switches
• What is the difference between JFET and BJT?

Field Effect Transistors Dr G V Subbarao gvs0raos@kluniversity.in

 Field Effect Transistor

JFET MOSFET
MESFET
or
IGFET
n-Channel p-Channel

Enhancement Depletion
MOSFET MOSFET

n-Channel p-Channel n-Channel p-Channel

EMOSFET EMOSFET DMOSFET DMOSFET

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 N-channel JFET
– Major structure is n-type material (channel)
between embedded p-type material to form p-n
junction.

– In the normal operation of an n-channel device,

the Drain (D) is positive with respect to the
Source (S). Current flows into the Drain (D),
through the channel, and out of the Source (S).

– Because the resistance of the channel depends

on the gate-to-source voltage (VGS), the drain
current (ID) is controlled by that voltage

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 JFET Characteristics
1. Drain Characteristics
Vds to Id for a constant Vgs

2. Transfer Characteristics

Vgs to Id

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 N-channel JFET

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https://rajeev2007.github.io/Animation_based/Junction%20Field%20Effect%20Transistor%20Ani
mation.html

JFET-Drain Characteristics
1. Vgs =0; Vds =0
2. Vgs =0; Vds  0
• Linear potential drop across the channel.
• Depletion region penetrates more into channel nearer to
drain more than source.
• Drain current increases linearly till pinch-off voltage.
• Beyond pinch off voltage current remains constant (I DSS.)
• Channel resistance increases.
• After certain value JFET Breaks down
3. Vgs < 0; Vds  0 4. Vgs < 0; Vds  0
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 ID versus VDS

for VGS = 0 V and 0<VDS<|Vp|

JFET Characteristic Curve

 JFET Characteristic Curve
• For negative values of VGS, the gate-to-channel junction is reverse
biased even with VDS=0
• Thus, the initial resistance of channel is higher.
• The resistance value is under the control of VGS
• If VGS = pinch-off voltage(VP)
• The device is in cutoff (VGS=VGS(off) = VP)
• The region where ID constant – the saturation/pinch-off region
• The region where ID depends on VDS is called the linear/ohmic
region
N-Channel JFET characteristics

Ohmic Saturation
 Transfer Characteristics

JFET Transfer Characteristic Curve JFET Characteristic Curve

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 Transfer Characteristics..
In JFET, the relationship between VGS (input voltage) and
ID (output current) is used to define the transfer
characteristics. It is called as Shockley’s Equation:
2
 VGS 
ID = IDSS  1 -  VP=VGS (OFF)
 VP 

Is it a square law device?

Field Effect Transistors Dr G V Subbarao gvs0raos@kluniversity.in

 Transfer Characteristics…
• Defined by Shockley’s equation:
2
 V 
I D  I DSS 1  GS  VP  VGS ( off )
 VGS 
 ( off ) 

• Relationship between ID and VGS.

• Obtaining transfer characteristic curve axis point from

Shockley:
– When VGS = 0 V, ID = IDSS
– When VGS = VGS(off) or Vp, ID = 0 mA

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 DC Load Line
The dc load line for a JFET can be
easily drawn by remembering the
following two points
(i) At ID = 0,
VDS = VDD
(ii) At VDS = 0,
ID = VDD/RD
Q Point is situated in the middle of
the load line  VDD 
VDD  
2
VDSQ 
2 I DQ  
RD
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 Problem

Estimate Quiescent point of

the circuit

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 Session 2

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 Biasing of JFET
Fixing VDS and ID

Biasing methods
1. Fixed Bias
2. Voltage Divider bias
3. Self bias

Field Effect Transistors Dr G V Subbarao gvs0raos@kluniversity.in

 Fixed Bias
IG =0  VGS = -VGG

2 2
 VGS   VGG 
I D =I DSS 1-   I DSS 1+  ..(1)
 VP   VP 

VDD -I D R D -VDS =0
VDS  VD  VDD -I D R D ...(2)

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 Problem
Determine the following for the network of Fig.
6.6.
(a) VGSQ. =-2V
(b) IDQ. =5.625mA
=4.75V
(c) VDS.
= 4.75V
(d) VD.
(e) VG. =-2V
=0V
(f) VS.
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 Voltage Divider Bias

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 Problem

Determine the following

for the network of Fig.
(a) IDQ = 2.4mA
= -1.8V
(b)VGSQ.
= 10.24V
(c) VD.
(d) VS. = 3.6V
= 6.64V
(e) VDS.
(f) VDG. = 8.42V
Field Effect Transistors Dr G V Subbarao gvs0raos@kluniversity.in
 Determine the following for
the network of Fig.
(a) IDQ and VGSQ.
(b) VDS.
(c) VD.
(d) VS.

Assess the difference between the remaining biasing circuits and this
ckt?
Field Effect Transistors Dr G V Subbarao gvs0raos@kluniversity.in
 Modeling of JFET
Small signal- low frequency modeling parameters
1.Transconductance
ΔI D -2 I DSS  VGS  -2 I DSS ID
gm = = 1 -  =
ΔVGS V Constant VP  VGS(off)  VP IDSS
DS

2. Dynamic drain resistance or Drain to source resistance

(slope of the drain characteristic in the pinch-off region and inverse of the
output admittance yos) 1 ΔVDS
r = d 
yos ΔI D VG SConstant

3. Amplification factor ΔVDS

μ= =g m rd
ΔVGS ID Constant

VDS
4. DC Drain resistance R DS =
ID
Field Effect Transistors Dr G V Subbarao gvs0raos@kluniversity.in
 Problem
a. For an N-channel JFET, IDSS = 8.7
mA, VP = –3 V, VGS = –1 V. Find the
values of
(i) ID
=3.87mA
(ii) gm =3.87mS

b. Determine the magnitude of g m for a

JFET with IDSS= 8mA and VP =4 V
at the following dc bias points:
(a) VGS=0.5 V. =3.5mS
(b) VGS=1.5 V. =2.57mS
(c) VGS=2.5 V. =1.5mS

Field Effect Transistors Dr G V Subbarao gvs0raos@kluniversity.in

 SMALL-SIGNAL
LOW FREQUENCY MODEL
1. The gate-to-source voltage controls the drain-to-source
(channel) current of an FET.

Δ I D =g m ΔVGS  id =g m vgs
2. Channel Resistance exists between drain and source

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 SMALL-SIGNAL
HIGH FREQUENCY MODEL
Need for Introducing other elements
1. Various regions of JFET structure acts as a parallel plate
capacitors

What are they … Guess?

(Cgs, Cds, Cgd and Cgs >> Cds ), To be modeled as Voltage
Cgso Cgdo
dependant capacitors. Cgs = m ; C gd = m
 Vgs   Vgd 
 1+   1+ 
 ψ0   ψ0 

2.The majority carriers require a finite transition time to cross the

source to gate channel.
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 Equivalent Circuit

Field Effect Transistors Dr G V Subbarao gvs0raos@kluniversity.in

 CS FET Amplifier- Fixed bias
(Low/Mid frequency and small signal)

Zi =R G A v = - g m (rd / / R D )  - g m R D
Zo = R D // rd  R D rd  10R D 
Field Effect Transistors Dr G V Subbarao gvs0raos@kluniversity.in
 Problem
The fixed-bias configuration of Example 6.1 had
an operating point defined by VGSQ=2 V and
IDQ = 5.625 mA, with IDSS =10 mA and VP8 V.
The network is redrawn as Fig. 9.14 with an
applied signal Vi. The value of yos is provided as
40 S. =1.88mS
(a) Determine gm. = 25kΩ
(b) Find rd. = 1MΩ
(c) Determine Zi. = 1.85kΩ
(d) Calculate Zo. =-3.48
(e) Determine the voltage gain Av.
(f) Determine
=-3.86
Av ignoring theDreffects of rd.
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 Enhancement MOSFET
Metal

SiO2
Source

P type Substrate
Channel

Drain
Appearing like two diodes connected back to back
Field Effect Transistors Dr G V Subbarao gvs0raos@kluniversity.in
 Circuit Symbol

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 E-MOSFET-Drain Characteristics
1. Vgs =0; Vds =0
2. Vds =0; Vgs  0.. Creating Channel
• Formation of inversion layer
• At Vgs=Vt sufficient number charges available to form
channel. i.e 0<Vgs<Vt Cut off region
• For over drive voltage Vgs>Vt , a proportionate charge will
3. be induced
V >Vin;the
gs
channel
0 <V t ds 
 V -V ...Linear ohmic
gs t 
W
Id =2 k n (VGS -Vt )VDS ; k n   n Cox
L
4.  
Vgs >Vt ; 0 < large Vds  Vgs -Vt ... Non Linear ohmic
5.  
Vgs >Vt ;Vds  Vgs -Vt ...Channel Pinch off, Saturation Id =k n (VGS -Vt ) 2
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Field Effect Transistors Dr G V Subbarao gvs0raos@kluniversity.in
 Depletion MOSFET

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Field Effect Transistors Dr G V Subbarao gvs0raos@kluniversity.in
 Other effects
Body effect
• Body connected to Source
• Connected to the most negative power supply.
– Depletion region will be widened
– Reduces Channel depth
– Resulting in an increase in threshold Voltage
Temperature Effect
Threshold Voltage decreases by 2 mV/0C

Field Effect Transistors Dr G V Subbarao gvs0raos@kluniversity.in

 MOSFET Biasing
Fixing VGS Fixing VGS and a Drain to Gate resistance
Fix VGS to get resistance at source
the required ID

If IG =0 
I D RD  VGS  VDD

I D  VGS  ID  I D  VGS  I D 
Field Effect Transistors Dr G V Subbarao gvs0raos@kluniversity.in
 Concept of V A
Feedback
o 1 T
Close loop gain: A CL = = = ( )
Vs 1+ Aβ β 1+ T
YourGain
Loop mother
: Tprepared
= A  β potato curry yesterday.
She is interested in your opinion on it. How did
Feedba ck factor or return difference : 1+ A  β
she know?
Feedback in Amplifiers
Vε = Vs  Vf
Vf = β  Vo
Vs Ve Vε = VS  β  Vo
Vo = A  Vε
A : Open Loop Gain; A = Vo / V

 : feedback factor;  = V / Vo
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gvs0raos@kluniversity.in
 Types of Feedback
• Negative feedback
Vo A
Vε = Vs  Vf  A CL = =
V 1+ Aβ
– Useful for normal amplifier applications due to
s

various of advantages.
• Positive Feedback
Vo A
Vε = Vs  Vf  A CL = =
Vs 1 - Aβ
– Useful for Oscillator applications with Aβ  1

Field Effect Transistors Dr G V Subbarao gvs0raos@kluniversity.in

 Advantages of negative feedback

• De sensitivity of the gain

• Increases the bandwidth of the amplifier
• Modify the input impedance based on topology
• Modify the output impedance based on topology
• Reduction in noise.
• Reduces phase distortion

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 Sampling

Output Impedance:Decreases Increases

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 Mixing

Input Impedance: Increases Decreases

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 Topologies
• Voltage amplifier---series-shunt feedback
voltage mixing and voltage sampling
• Current amplifier---shunt-series feedback
Current mixing and current sampling
• Transconducatnce amplifier---series-series
feedback
Voltage mixing and current sampling
• Transresistance amplifier---shunt-shunt feedback
Current mixing and voltage sampling
Field Effect Transistors Dr G V Subbarao gvs0raos@kluniversity.in
 Voltage sampling & Voltage mixing

Sampling : Voltage (Shunt)

Mixing : Voltage (Series)

Voltage-mixing voltage-sampling (series–shunt) topology

Voltage Amplifier
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 Current Series Amplifier

Sampling : Current (Series)

Mixing : Voltage (Series)

Series- Series or Current-series topology

Trans conductance Amplifier
Field Effect Transistors Dr G V Subbarao gvs0raos@kluniversity.in
 How to identify topology?
Sampling:
– Make output voltage zero(Short the o/p), if feedback
component become zero… Voltage sampling
– Make output current zero(open the o/p), if feedback
component become zero… Current sampling
Mixing:
– Observe the voltage zero(Short the o/p), if feedback
component become zero… Voltage sampling
– Make output current zero(open the o/p), if feedback
component become zero… Current sampling
Field Effect Transistors Dr G V Subbarao gvs0raos@kluniversity.in
 Current-Shunt topology

Sampling : Current (Series)

Mixing : Current(Shunt)

Current- Shunt or Shunt –Series Topology

Current Amplifier

Field Effect Transistors Dr G V Subbarao gvs0raos@kluniversity.in