Adc Design
Adc Design
Adc Design
Voltage
Integer N Controlled Non-Overlapping Clock Input/Output
Divider Oscillator
N 991 - 998 MH z or
CLK
1011-1018 MHz
N
AN
Trained
P2: Multichannel Phase Locked Loop P3: 25MSPS, 8-bit Two Stage ADC
FM Tx 2
102 MHz
101-108 1001-1008
MHz MHz
LNA Amp
FM Transmission Module
Chip 1
P1: 1GHz FM Radio Receiver
Voltage
Integer N Controlled Non-Overlapping Clock Input/Output
Divider Oscillator
N 991 - 998 MH z or
CLK
1011-1018 MHz
N
AN
Trained
P2: Multichannel Phase Locked Loop P3: 25MSPS, 8-bit Two Stage ADC
• Many Other very important Performance Parameters like SNR, Offset, Power, INL/DNL etc.
• But for the sake of simplicity we will ignore them here.
• We will see them during design
Proposed ADC Architecture
++--
A/D 4-bit A/D 4-bit
Mux D/A 16
MSB LSB
Non-Overlapping Clock
CLK
Let’s get down to technicalities…….!
• Target Schematic design will be at 33MSPS!!!......WHY??
• Layout Parasitic delays will inevitably slow down the circuit.
• Design margin of speed in schematic will help us compensate that
delay without doing too many layout iterations.
Timing Constraints
15ns
• Fclk=33MSPS => Tclk=30ns (50% Duty Cycle)
• Tracking/Sampling Time= 30/2 =15ns
• Hold/Conversion Time=15ns
• Our conversion must complete within 15ns at all
process corners and temperature range
15ns
Timing Distribution
15 ns 4 ns 4 ns 3 ns 4 ns
++--
A/D 4-bit A/D 4-bit
Sample/ D/A 16
Hold MSB LSB
Non-Overlapping Clock
Switch
• A capacitor to hold charge IN OUT
• Very Simple
MSB
• Requires Comparators
• Guaranteed Monotonicity
• Encoder required
Thermometer
code
• Conversion time <= 4ns
LSB
Resistor String DAC
VREF
• Very Simple
• Uses thermometer Code
• Guaranteed Monotonicity
• Compatible with our ADC
• Conversion time <= 4ns
Vout
Subtractor and Multiplication
R
• Opamp based subtraction
• Opamp based multiplication R Vout
V2
V1 V1-V2
• All resistors are equal R
• All resistors must match in layout R