EE382V Fall 2006

VLSI Physical Design Automation

Lecture 9. Introduction to Routing;

Global Routing (I)

Prof. David Pan

dpan@ece.utexas.edu
Office: ACES 5.434

10/18/08 1
Introduction to Routing

10/18/08 2
 Routing in design flow
B

A C
Netlist

INV

Routing
AND
OR

Floorplan/Placement
3
 The Routing Problem
• Apply it after floorplanning/placement
• Input:
– Netlist
– Timing budget for, typically, critical nets
– Locations of blocks and locations of pins
• Output:
– Geometric layouts of all nets
• Objective:
– Minimize the total wire length, the number of vias, or just
completing all connections without increasing the chip area.
– Each net meets its timing budget.

4
 The Routing Constraints
• Examples:
– Placement constraint
– Number of routing layers
– Delay constraint
– Meet all geometrical constraints (design rules)
– Physical/Electrical/Manufacturing constraints:
• Crosstalk
• Process variations, yield, or lithography issues?

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 Steiner Tree
• For a multi-terminal net, we can construct a
spanning tree to connect all the terminals
together.
• But the wire length will be large.
• Better use Steiner Tree:
A tree connecting all terminals and some Steiner
additional nodes (Steiner nodes). Node
• Rectilinear Steiner Tree:
Steiner tree in which all the edges run horizontally
and vertically.

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 Routing Problem is Very Hard

• Minimum Steiner Tree Problem:

– Given a net, find the Steiner tree with the minimum length.
– This problem is NP-Complete!
• May need to route tens of thousands of nets
simultaneously without overlapping.
• Obstacles may exist in the routing region.

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Kinds of Routing

• Global Routing
• Detailed Routing
– Channel
– Switchbox
• Others:
– Maze routing
– Over the cell routing
– Clock routing

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 Approaches for Routing
• Sequential Approach:
– Route nets one at a time.
– Order depends on factors like criticality, estimated wire length, and
number of terminals.
– When further routing of nets is not possible because some nets
are blocked by nets routed earlier, apply ‘Rip-up and Reroute’
technique (or ‘Shove-aside’ technique).
• Concurrent Approach:
– Consider all nets simultaneously, i.e., no ordering.
– Can be formulated as integer programming.

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Classification of Routing

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 General Routing Paradigm
Two phases:

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 Extraction and Timing Analysis

• After global routing and detailed routing, information of

the nets can be extracted and delays can be analyzed.
• If some nets fail to meet their timing budget, detailed
routing and/or global routing needs to be repeated.

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 Global Routing

Global routing is divided into 3 phases:

1. Region definition
2. Region assignment
3. Pin assignment to routing regions

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 Region Definition
Divide the routing area into routing regions of simple shape
(rectangular):

Switchbox
Channel

• Channel: Pins on 2 opposite sides.

• 2-D Switchbox: Pins on 4 sides.
• 3-D Switchbox: Pins on all 6 sides.

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Routing Regions

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 Routing Regions in
Different Design Styles

Gate-Array Standard-Cell Full-Custom

Feedthrough Cell
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 Region Assignment
Assign routing regions to each net. Need to consider timing
budget of nets and routing congestion of the regions.

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 Graph Modeling of
Routing Regions

• Grid Graph Modeling

• Checker Board Graph Modeling
• Channel Intersection Graph Modeling

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 Grid Graph

A terminal A node with terminals

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 Checker Board Graph
capacity

1 1 1

2 2 1 1
1 1 1

A terminal A node with terminals

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Channel Intersection Graph

A terminal A node with terminals

Routings along the channels

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 Approaches for Global Routing

Sequential Approach:
– Route the nets one at a time.
– Order dependent on factors like criticality, estimated wire
length, etc.
– If further routing is impossible because some nets are
blocked by nets routed earlier, apply Rip-up and Reroute
technique.
– This approach is much more popular.

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 Approaches for Global Routing

Concurrent Approach:
– Consider all nets simultaneously.
– Can be formulated as an integer program.

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 Pin Assignment
Assign pins on routing region boundaries for each net.
(Prepare for the detailed routing stage for each region.)

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25
Maze Routing

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 Maze Routing Problem
• Given:
– A planar rectangular grid graph.
– Two points S and T on the graph.
– Obstacles modeled as blocked vertices.
• Objective:
– Find the shortest path connecting S and T.
• This technique can be used in global or detailed
routing (switchbox) problems.

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 Grid Graph

S S
S 

T X X 
T
X X  T

Area Routing Grid Graph Simplified

(Maze) Representation

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 Maze Routing

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 Lee’s Algorithm

“AnAlgorithm for Path Connection and its Application”,

C.Y. Lee, IRE Transactions on Electronic Computers,
1961.

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 Basic Idea
• A Breadth-First Search (BFS) of the grid graph.
• Always find the shortest path possible.
• Consists of two phases:
– Wave Propagation
– Retrace

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An Illustration

S
0 1 2 3
1 2 3
3 4 5
T
5 4 5 6

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 Wave Propagation
• At step k, all vertices at Manhattan-distance k from S
are labeled with k.
• A Propagation List (FIFO) is used to keep track of the
vertices to be considered next.

S S S
0 0 1 2 3 0 1 2 3
1 2 3 1 2 3
3 3 4 5
T T T
5 4 5 6
After Step 0 After Step 3 After Step 6 33
 Retrace
• Trace back the actual route.
• Starting from T.
• At vertex with k, go to any vertex with label k-1.

S
0 1 2 3
1 2 3
3 4 5
T
5 4 5 6
Final labeling
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How many grids visited using Lee’s algorithm?

13 121110 7 6 7 7 9 10
12 1110 9 6 5 6 7 8 9 101112
1110 9 8 7 6 5 4 7 8 9 1011
10 9 8 7 6 5 4 3 6 7 8 9 10
7 6 54 3 2 1 2 3 4 5 67 8 9
6 5 4 3 2 1 S1 23 4 5 6 7 8
9 8 7 6 3 2 1 2 3 4 5 6 78 9
10 9 8 7 3 5 6 7 8 9 10
1110 9 8 9 10 76 7 8 9 1011
12 11 10 11121110 9 8 9 101112
13 12 11121312 1110 9 10111213
12 13 1312 1110 111213
13 13 1211 1213
1312 T 13
13
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 Time and Space Complexity

• For a grid structure of size w × h:

• Time per net = O(wh)
• Space = O(wh log wh) (O(log wh) bits are needed to store
each label.)
• For a 4000 × 4000 grid structure:
• 24 bits per label
• Total 48 Mbytes of memory!

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Improvement to Lee’s Algorithm
• Improvement on memory:
– Aker’s Coding Scheme
• Improvement on run time:
– Starting point selection
– Double fan-out
– Framing
– Hadlock’s Algorithm
– Soukup’s Algorithm

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 Aker’s Coding Scheme
to Reduce Memory Usage

10/18/08 38
 Aker’s Coding Scheme

• For the Lee’s algorithm, labels are needed during

the retrace phase.
• But there are only two possible labels for neighbors
of each vertex labeled i, which are, i-1 and i+1.
• So, is there any method to reduce the memory
usage?

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 Aker’s Coding Scheme

One bit (independent of grid size) is enough to

distinguish between the two labels.

S Sequence:
...… (what sequence?)

(Note: In the sequence, the

labels before and after each
T label must be different in
order to tell the forward or
the backward directions.)
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 Schemes to Reduce Run Time
1. Starting Point Selection:

T S
S T

2. Double Fan-Out: 3. Framing:

S S
T T

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Hadlock’s Algorithm
to Reduce Run Time

10/18/08 42
 Detour Number
For a path P from S to T, let detour number d(P) = #
of grids directed away from T, then
L(P) = MD(S,T) + 2d(P)

length
shortest Manhattan distance
D D
D: Detour
D
S d(P) = 3
MD(S,T) = 6
T L(P) = 6+2x3 = 12

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So minimizing L(P) and d(P) are the same.
 Hadlock’s Algorithm
• Label vertices with detour numbers.
• Vertices with smaller detour number are expanded
first.
• Therefore, favor paths without detour.

3 2 2 2 2 2 2
2 1 1 2 2
1 S 0 2
1 0 0
1 0 0 2 T
2 1 1 2 2
3 2 2 2 2 2
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 Soukup’s Algorithm
to Reduce Run Time

10/18/08 45
 Basic Idea
• Soukup’s Algorithm: BFS+DFS
– Explore in the direction towards the target without changing
direction. (DFS)
– If obstacle is hit, search around the obstacle. (BFS)
• May get Sub-Optimal solution.

2
2 1
1 S 1
1 1
1 T
2 1 1
2 2
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How many grids visited using Hadlock’s?

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How many grids visited using Soukup’s?

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 Multi-Terminal Nets

• For a k-terminal net, connect the k terminals using a

rectilinear Steiner tree with the shortest wire length on
the maze.
• This problem is NP-Complete.
• Just want to find some good heuristics.

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 Multi-Terminal Nets

This problem can be solved by extending the Lee’s

algorithm:
– Connect one terminal at a time, or
– Search for several targets simultaneously, or
– Propagate wave fronts from several different sources
simultaneously.

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Extension to Multi-Terminal Nets

1st Iteration 2nd Iteration

S S
0 1 2 T3 0 S0 S0 S0
2 3 1 1 1
T T
3 2 2 2

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