Chapter # 2:

Instructions: Language of the

Computer

Course Instructor: Dr. Afshan

Jamil
Lecture # 4
 Contents
Contents
• Instruction set
• Stored-program concept
• Operations of the computer hardware
• Operands of the computer hardware
• Load instruction
• Store instruction
• Spilling registers
• Constants or Immediate operand
• Constant 0
• Signed and unsigned numbers
• Instruction formats
Recall
 Instruction Set
• The words of a computer’s language are called instructions.
• The vocabulary of commands understood by a given architecture is called instruction
set.
• Computer languages are quite similar.
• Just like computer languages, instruction sets are also similar because
– All computers are constructed from hardware technologies based on similar
– underlying principles.
– There are a few basic operations that all computers must provide.
– Computer designers have a common goal: to find a language that makes it easy to
build the hardware and the compiler while maximizing performance and minimizing
cost and energy.
• Following quote was written in 1947 and it is as true today as it was in 1947:

It is easy to see by formal-logical methods that there exist certain [instruction sets] that are
in abstract adequate to control and cause the execution of any sequence of operations.…
The really decisive considerations from the present point of view, in selecting an
[instruction set], are more of a practical nature: simplicity of the equipment demanded by
the [instruction set], and the clarity of its application to the actually important problems
together with the speed of its handling of those problems.
[Burks, Goldstine, and von Neumann]
Stored-program concept
• The idea that instructions and data of many
types can be stored in memory as numbers and
thus be easy to change, leading to the stored-
program computer.
• Treating instructions in the same way as data
greatly simplifies both the memory hardware
and the software of computer systems.
Operations of the computer hardware

• Design Principle 1: Simplicity favors regularity

• Every computer must perform arithmetic operations.
• RISC-V requires every instruction to perform single operation
and have exactly three operands/variables, no more and no
less, to keep the hardware simple
• Hardware for a variable number of operands is more
complicated than hardware for a fixed number.
• Operand order is fixed (e.g., destination first)
Operations of the computer Hardware
• Example 1:
C code: a = b + c

RISC-V code: add a, b, c

• Example 2:
C code: a = b + c + d + e
RISC-V code:
add a, b, c // a=b+c
add a, a, d // a=a+d
add a, a, e // a=a+e

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 CONTD…
• Example 3:
C code: a = b + c;
d = a – e;
RISC-V code: add a, b, c
sub d, a, e
• Example 4:
C code: f = (g + h) – (i + j);
RISC-V code:
add t0,g,h //temporary variable t0 contains g + h
add t1,i,j //temporary variable t1 contains i + j
sub f,t0,t1
Operands of the Computer Hardware
• Design Principle 2: Smaller is faster
– Arithmetic instructions operands must be in registers
– Size of register is 64 bits (group of 64 bits is called doubleword)
– RISC-V has 32 registers. Reasons of keeping only 32 registers are:
1. A very large number of registers may increase the clock cycle time.
2. The number of bits it would take in the instruction format.
– The RISC-V convention is x followed by the number of the register.

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Example

• Example 1: f = (g + h) – (i + j);
The variables f, g, h, i, and j are assigned to the registers
x19, x20, 221, x22 and x23 respectively.
add x5,x20,x21
add x6,x22,x23
sub x19,x5,x6
RISC-V Register conventions
Memory operands

• What about programs with lots of variables (arrays and structures)?

– Use memory,
• Remember RISC-V arithmetic operands are registers, not memory
locations.
• RISC-V must include instructions that transfer data between memory
and registers.
• Such instructions are called data transfer instructions.
• Memory is just a large, single-dimensional array, with the address acting
as the index to that array, starting at 0.

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Memory addresses and contents of memory at those addresses
CONTD…
• Since 8-bit bytes are useful in many programs, virtually all architectures today
address individual bytes. Therefore, the address of a doubleword matches the address
of one of the 8 bytes within the doubleword, and addresses of sequential
doublewords differ by 8.
Load Instruction

“Used to load a doubleword from memory”

• The real RISC-V name for this instruction is ld, standing for load
doubleword
• ld x1, offset(x2)
• The address is computed by adding the contents of register x2 to
the sign-extended offset (which is an immediate value).
• Value from address computed above is then loaded into register x1
• Example:
• ld x6, 20(x19) // x6 = Memory[x19 + 20]

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STORE Instruction
“Used to store a doubleword to memory”
• The actual RISC-V name for this instruction is sd, standing for store
doubleword.
• sd x1, offset(x2)
• The address is computed by adding the contents of register x1 to the
sign-extended offset (which is an immediate value).
• Value from register x2 is then copied to the memory address computed.
• Example:
• sd x6, 20(x19) // Memory[x19+ 20] = x6

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 CONTD…

• Example 1: g = h + A[8];
ld x9,64(x22) // Temporary reg x9 gets A[8]
add x20,x21,x9 // g = h + A[8]

• Example 2: A[12] = h + A[8];

ld x9,64(x22) // Temporary reg x9 gets A[8]
add x9,x22,x9 // Temporary reg x9 gets h + A[8]
sw x9,96(x22) // Stores h + A[8] back into
A[12]
Spilling registers
• Many programs have more variables than computers have registers.
• Consequently, the compiler tries to keep the most frequently used variables in
registers and places the rest in memory.
• The process of putting less commonly used variables (or those needed later) into
memory is called spilling registers.
• Registers take less time to access and have higher throughput than memory, making
data in registers both faster to access and simpler to use.
• Accessing registers also uses less energy than accessing memory.
• To achieve highest performance and conserve energy, an instruction set architecture
must have sufficient number of registers, and compilers must use registers
efficiently.
Constant or Immediate Operand
• Constant operands occur frequently in arithmetic instructions.
• An immediate instruction uses a constant number as one of the inputs (instead
of a register operand).
• Operations are much faster and use less energy than if constants were loaded
from memory.
• Design Principle 3: Make the common case fast
• Example:
addi x19, x20, 4
• There is no “subtract immediate” instruction ! Subtract is “add a negative”
addi x19, x20, -4

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Constant 0

• RISC-V dedicates a register x0 to be hard-wired to the value

zero.
• Cannot be overwritten !
• Useful for common operations ! e.g., move between registers
add x9, x10, x0

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To keep the examples simple, in this book all pointers are assumed to be 64 bits
and all C integers are assumed to be declared as long long int to keep them the
same size.
Signed and unsigned numbers

• Numbers are kept in computer hardware as a series of high and low electronic
signals, and so they are considered base 2 numbers.
• Base 2 numbers are called binary numbers.
• A single digit of a binary number is thus the “atom” of computing, since all
information is composed of binary digits or bits.
• This fundamental building block can be one of two values, which can be thought of
as several alternatives: high or low, on or off, true or false, or 1 or 0.
• In any number base, the value of ith digit d is ,where i starts at 0 and
increases from right to left.
CONTD…

Example:

Represents
 RISC-V doubleword

• The phrase least significant bit is used to refer to the rightmost bit (bit 0 above) and
most significant bit to the leftmost bit (bit 63).
 CONTD…

• The RISC-V doubleword is 64 bits long, so we can represent different 64-bit patterns.
• 64-bit binary numbers can be represented in terms of the bit value times a power of 2
(here means the ith bit of x):

• Keep in mind that the binary bit patterns above are simply representatives of
numbers. Numbers really have an infinite number of digits, with almost all being 0
except for a few of the rightmost digits. We just don’t normally show leading 0s.
• If result of arithmetic operations cannot be represented by these rightmost
hardware bits, overflow is said to have occurred. It’s up to the programming
language, the operating system, and the program to determine what to do if
overflow occurs.
CONTD…
• Computer programs calculate both positive and negative numbers, so we need a
representation that distinguishes the positive from the negative.
• The representation that made the hardware simple is two’s complement
representation: leading 0s mean positive, and leading 1s mean negative.
• Two’s complement representation has the advantage that all negative numbers have a
1 in the most significant bit. Thus, hardware needs to test only this bit to see if a
number is positive or negative (with the number 0 is considered positive). This bit is
often called the sign bit.
• Overflow occurs when the sign bit is incorrect): a 0 on the left of the bit pattern when
the number is negative or a 1 when the number is positive.
Two’s complemet
• =
Negating this number by inverting the bits and adding one,

Going the other direction

• =
Negating this number by inverting the bits and adding one,

+
 Sign extension
• How to convert a binary number represented in n bits to a number represented with more than n bits.
• Take the most significant bit from the smaller quantity—the sign bit—and replicate it to fill the new
bits of the larger quantity.
• The 16-bit binary version of the number 2 is

• It is converted to a 64-bit number by making 48 copies of the value in the most significant bit (0)
and placing that in the left of the doubleword. The right part gets the old value:
• =
• If we negate this number using two’s complement method

• Creating a 64-bit version of the negative number means copying the sign bit 48 times and placing it
on the left:
• =
Binary to Hexadecimal
Instruction Formats
• All RISC-V instruction takes exactly 32 bits—the same size as a data word.
• There is a conflict between the desire to keep all instructions the same length and
the desire to have a single instruction format. This leads us to the final hardware
design principle:
• Design Principle 4: Good design demands good compromises.
• The compromise chosen by the RISC-V designers is to keep all instructions the same
length, thereby requiring different kinds of instruction formats for different kinds of
instructions.
• R-format
• I-format
• S-format

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R-format

Instruction fields !
• op: Basic operation code (opcode).
• rd: destination register number. It gets the result of the operation.
• funct3: An additional opcode field.
• rs1: The first register source operand.
• rs2: The second register source operand.
• funct7: An additional opcode field.
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I-format

• Immediate arithmetic and load doubleword instruction.

• op: operation code (opcode) !
• rs: first source register number !
• rd: destination register number !
• immediate: offset added to base address in rs or a two’s
complement constant in case of addi.

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S-format

Store doubleword instruction.

• op: operation code (opcode).
• rs1: first source register number.
• rs2: second source register number.
• rd: destination register number !
• immediate: offset added to base address in rs or a two’s
complement constant in case of addi.
Example

• A[30] = h + A[30] + 1;
is compiled into
• ld x9, 240(x10) // Temporary reg x9 gets A[30]
• add x9, x21, x9 // Temporary reg x9 gets h+A[30]
• addi x9, x9, 1 // Temporary reg x9 gets h+A[30]+1
• sd x9, 240(x10) // Stores h+A[30]+1 back into A[30]

• RISC-V machine code for these instructions

Machine language instructions
Thanks