Mips Instruction Format
Mips Instruction Format
Mips Instruction Format
Instructions: Overview
MIPS Arithmetic
Example:
C code:
A = B + C
MIPS code:
MIPS Arithmetic
Instructions are regular which make simple hardware! And Simpler
hardware reduces design time and manufacturing cost.
Operands must be in registers only 32 registers provided
(which require 5 bits to select one register).
But this complicates code translation..
C code:
A = B + C + D;
E = F - A;
MIPS code add $t0, $s1, $s2
(arithmetic):
add $s0, $t0, $s3
sub $s4, $s5, $s0
Input
Memory
Datapath
Processor
Output
I/O
Memory Organization
8 bits of data
8 bits of data
3
4
5
6
8 bits of data
8 bits of data
8 bits of data
8 bits of data
8 bits of data
...
Memory Organization
Bytes are load/store units, but most data items use larger
words
For MIPS, a word is 32 bits or 4 bytes.
0
4
8
12
32 bits of data
32 bits of data
32 bits of data
32 bits of data
...
Load/Store Instructions
A[8] = h + A[8];
lw $t0, 32($s3)
add $t0, $s2, $t0
sw $t0, 32($s3)
MIPS
loading words but addressing bytes
arithmetic on registers only
Instruction
Meaning
Instruction Formats
Instruction
Format
R-type
(R
for aRithmetic):
000000
1000
10010
01000
00000 100000
1 rs
op
rt
rd
shamt
funct
opcode
operation
6 bits
first
register
source
operand
second
register
source
operand
5 bits
5 bits
register shift
destin- amount
ation
operand
5 bits
5 bits
6 bits
Machine Language
rs
6 bits
bits
5 bits
01000
rt
0000001111101010
16 bit offset
5 bits
16
Processor
Memory
Memory Organization:
Big/Little Endian Byte Order
Little-endian
Memory
Bit 0
Bit 31
Big-endian
Memory
Bit 0
Bit 31
Example:
I-type instructions
0000000000011001
if (i==j) h = i + j;
Addresses in Branch
Instructions:
bne $t4,$t5,Label
beq $t4,$t5,Label
Format:
I
op
rs
rt
16 bit offset
Addresses in Branch
word-relative
Example: j Label # addr. Label = 100 addressing:
25 words = 100 byte
000010
6 bits
op
00000000000000000000011001
26 bits
26 bit number
Addresses in Jump
op
26 bit address
Constants
MIPS Instructions:
addi $29, $29, 4
slti $8, $18, 10
andi $29, $29, 6
ori $29, $29, 4
Immediate Operands
001000
6 bits
op
1110
1
5 bits
r
s
1110
1
5 bits
rt
000000000000010
0
16 bits
16 bit number
1010101010101010
0000000000000000
ori
1010101010101010
0000000000000000
0000000000000000
1010101010101010
1010101010101010
1010101010101010
So far
Instruction
Format
add $s1,$s2,$s3
sub $s1,$s2,$s3
lw $s1,100($s2)
sw $s1,100($s2)
bne $s4,$s5,Lab1
beq $s4,$s5,Lab2
j Lab3
R
R
I
I
I
I
J
Meaning
$s1 = $s2 + $s3
$s1 = $s2 $s3
$s1 = Memory[$s2+100]
Memory[$s2+100] = $s1
Next instr. is at Lab1 if $s4 != $s5
Next instr. is at Lab2 if $s4 = $s5
Next instr. is at Lab3
Formats:
R
op
rs
rt
rd
op
rs
rt
16 bit address
op
shamt
26 bit address
funct
Control Flow
New instruction:
if $s1 < $s2 then
$t0 = 1
slt $t0, $s1, $s2
$t0 = 0
else
Usage
the constant value 0
values for results and expression evaluation
arguments
temporaries
saved
more temporaries
global pointer
stack pointer
frame pointer
return address
Procedures
Example C code:
Procedures
Translated MIPS assembly
main:
addi $s0, $0, 5
add $a0, $s0, $0
save register
in stack, see
figure below
add10:
addi $sp, $sp, -4
sw $s0, 0($sp)
jal add10
result
control
returns here to caller
li
$v0,
10
jump and link
restore lw $s0, 0($sp)
syscall
values addi $sp, $sp,
return
system code
& call to
$sp
exit
jr $ra
High address
MEMOR
Y
Content of $s0
Low address
MIPS: Software
Conventions
zero constantfor
0
16 s0 callee saves
Registers
at
23 s7
v1 returned to caller
24 t8
a0 arguments to callee
25 t9
a1
a2
27 k1
a3
t0
...
15 t7
...
temporary (contd)
29 sp stack pointer
30 fp
frame pointer
31 ra
Procedures (recursive)
int main()
{ int i;
i = 4;
j = fact(i);
return 0;}
int fact(int n)
{ if (n < 1) return (1);
else return ( n*fact(n-1) );}
Procedures (recursive)
main:
main
branch to
L1 if n>=1
return 1
if n < 1
control li $v0, 1
returns syscall
from fact li $v0, 10
syscall
print value
fact:
returned by addi $sp, $sp, -8
sw $ra, 4($sp)
fact
sw $a0, 0($sp)
exit
L1:
if n>=1 call
fact recursively
with argument
n-1
restore return
address, argument,
and stack pointer
save return
address and
argument in
stack
return
n*fact(n-1)
return control
Run this code with PCSpim: factorialRecursive.asm
$fp
$sp
$sp
$fp
Saved argument
registers (if any)
Saved return address
Saved saved
registers (if any)
Low address
a.
b.
c.
Variables that are local to a procedure but do not fit into registers (e.g., local arrays, s
tures, etc.) are also stored in the stack. This area of the stack is the frame. The frame
$fp points to the top of the frame and the stack pointer to the bottom. The frame poin
not change during procedure execution, unlike the stack pointer, so it is a stable base
register from which to compute offsets to local variables.
Use of the frame pointer is optional. If there are no local variables to store in the stack
not efficient to use a frame pointer.
Exercise:
Modify procCallsProg1Modified.asm to use a frame pointer
Observe that SPIM names register 30 as s8 rather than fp. Of
course, you can use it as fp, but make sure to initialize it with
the same value as sp, i.e., 7fffeffc.
rs
rt
Immediate
2. Register addressing
op
rs
rt
rd
...
funct
Registers
Register
3. Base addressing
op
rs
rt
Memory
Address
Register
Byte
Halfword
4. PC-relative addressing
op
rs
rt
Memory
Address
PC
Word
5. Pseudodirect addressing
op
Address
PC
Memory
Word
Word
Overview of MIPS
op
rs
rt
rd
op
rs
rt
16 bit address
op
funct
26 bit address
shamt
Summarize MIPS:
MIPS operands
Name
32 registers
Example
Comments
$s0-$s7, $t0-$t9, $zero, Fast locations for data. In MIPS, data must be in registers to perform
$a0-$a3, $v0-$v1, $gp,
arithmetic. MIPS register $zero always equals 0. Register $at is
$fp, $sp, $ra, $at
reserved for the assembler to handle large constants.
Memory[0],
30
words
Memory[4294967292]
Arithmetic
Instruction
add
Example
add $s1, $s2, $s3
Meaning
$s1 = $s2 + $s3
subtract
Data transfer
Conditional
branch
Unconditional jump
$s1 = 100 * 2
16
Comments
branch on equal
beq
$s1, $s2, 25
if ($s1 == $s2) go to
PC + 4 + 100
bne
$s1, $s2, 25
if ($s1 != $s2) go to
PC + 4 + 100
slt
slti
jump
j
jr
jal
jump register
jump and link
else $s1 = 0
2500
$ra
2500
Alternative Architectures
Design alternative:
provide more powerful operations
goal is to reduce number of instructions executed
danger is a slower cycle time and/or a higher CPI
PowerPC Special
Instructions
Indexed addressing
Example:
lw $t1,$a0+$s3 #$t1=Memory[$a0+$s3]
what do we have to do in MIPS? add $t0, $a0, $s3
lw
$t1, 0($t0)
Update addressing
Others:
A dominant architecture:
80x86
1978: The Intel 8086 is announced (16 bit architecture)
1980: The 8087 floating point coprocessor is added
1982: The 80286 increases address space to 24 bits,
+instructions
1985: The 80386 extends to 32 bits, new addressing modes
1989-1995: The 80486, Pentium, Pentium Pro add a few
instructions (mostly designed for higher performance)
1997: MMX is added
this history illustrates the impact of the golden handcuffs of
compatibility
adding new features as someone might add clothing to a packed bag
A dominant architecture:
80x86
Complexity
Saving grace:
the most frequently used instructions are not too difficult to build
compilers avoid the portions of the architecture that are slow
Summary
Design Principles: