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Lecture 2 Top Level View of Computer Function and Interconnection

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24 views

Lecture 2 Top Level View of Computer Function and Interconnection

Uploaded by

syed.12682
Copyright
© © All Rights Reserved
Available Formats
Download as PPTX, PDF, TXT or read online on Scribd
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William Stallings

Computer Organization
and Architecture
8th Edition
Chapter 3
Top Level View of Computer Function
and Interconnection
Book by : Computer, Architecture and Organizations, 8th Edition ,William Stalling
Original Slides by : Adrian J Pullin
Top Level View of Computer
Function and Interconnection
Lecture Outcomes
Understanding of:
• Computer Components
• Computer Function
• Instruction Fetch and Execute
• Interrupts
Program Concept
What is an algorithm and program?
Algorithm:
An algorithm is a finite list of well-defined instructions that carries out an
operation
Program:
• A program is asset of computer instructions that implement an Al-
gorithm
• A sequence of steps
• For each step, an arithmetic or logical operation is done
• For each operation, a different set of control signals is needed
Function of Control Unit
• For each operation a unique code is provided
– e.g. ADD, MOVE
• A hardware segment accepts the code and issues the control
signals

• We have a computer!
Components
Computer Components : Top Level View
Instruction Cycle
Fetch Cycle
• Program Counter (PC) holds address of next instruction to
fetch
• Processor fetches instruction from memory location
pointed to by PC
• Increment PC
– Unless told otherwise
• Instruction loaded into Instruction Register (IR)
• Processor interprets instruction and performs required ac-
tions
Execute Cycle
Example of Program Execution
Instruction Cycle State Diagram
■■ Instruction fetch (if): Read instruction from its memory location into the
processor.

■■ Instruction operation decoding (iod): Analyze instruction to determine type


of operation to be performed and operand(s) to be used.

■■ Operand address calculation (oac): If the operation involves reference to an


operand in memory or available via I/O, then determine the address of the
operand.

■■ Operand fetch (of): Fetch the operand from memory or read it in from I/O.
■■ Data operation (do): Perform the operation indicated in the instruction.
■■ Operand store (os): Write the result into memory or out to I/O.
Interrupts
• Mechanism by which other modules (e.g. I/O) may interrupt normal
sequence of processing
• Program
– e.g. overflow, division by zero
• Timer
– Generated by internal processor timer
– Used in pre-emptive multi-tasking
• I/O
– from I/O controller
• Hardware failure
– e.g. memory parity error
Program Flow Control
Interrupt Cycle
• Added to instruction cycle
• Processor checks for interrupt
– Indicated by an interrupt signal
• If no interrupt, fetch next instruction
• If interrupt pending:
– Suspend execution of current program
– Save context
– Set PC to start address of interrupt handler routine
– Process interrupt
– Restore context and continue interrupted program
Interrupt handler
When the external device becomes ready to be serviced—that is,
when it is ready to accept more data from the processor—the I/O
module for that external device sends an interrupt request signal
to the processor. The processor responds by suspending opera-
tion of the current program, branching off to a program to ser-
vice that particular I/O device, known as an interrupt handler,
and resuming the original execution after the device is serviced.
Transfer of Control via Interrupts
Instruction Cycle with Interrupts
Program Timing Short I/O Wait
Instruction Cycle (with multiple interrupts) - State Diagram
Multiple Interrupts
Two approaches can be taken to dealing with multiple interrupts.
• Disable interrupts
– Processor will ignore further interrupts whilst processing one in-
terrupt
– Interrupts remain pending and are checked after first interrupt
has been processed
– Interrupts handled in sequence as they occur
• Define priorities
– Low priority interrupts can be interrupted by higher priority inter-
rupts
– When higher priority interrupt has been processed, processor
returns to previous interrupt
Multiple Interrupts - Sequential
Multiple Interrupts – Nested
Multiple Interrupts – Example
Review Questions
 What general categories of functions are specified by computer instructions?
List and briefly define the possible states that define an instruction execution.
List and briefly define two approaches to dealing with multiple interrupts.
Thank you

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