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    Shaikh Khaled Mostaque Assistant Professor Dept. of Electrical and Electronic Engineering University of Rajshahi

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    juhurabegum1956

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    Shaikh Khaled Mostaque Assistant Professor Dept. of Electrical and Electronic Engineering University of Rajshahi

    Uploaded by

    juhurabegum1956
    3 views8 pages

    Original Title

    8259A

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    3 views8 pages

    Shaikh Khaled Mostaque Assistant Professor Dept. of Electrical and Electronic Engineering University of Rajshahi

    Uploaded by

    juhurabegum1956

    Copyright:

    © All Rights Reserved
    Download as PPTX, PDF, TXT or read online from Scribd
    Download as pptx, pdf, or txt
    of 8

    8259A

    Shaikh Khaled Mostaque


    Assistant Professor
    Dept. of Electrical and Electronic Engineering
    University of Rajshahi
    What is programmable interrupt controller?

    • In a small system we may


    require a lots of interrupts
    • Each of the interrupts require a
    separate interrupt input
    • 8086 has only two interrupts

    • We use an external device called


    programmable interrupt
    controller.
    Interrupts • Three sources

    in 8086
    1. External signal applied to the
    nonmaskable interrupt input
    pin (NMI) or to the interrupt
    (INTR) input pin.
    2. Execution of interrupt
    instruction i.e. software
    interrupt
    3. Error condition produced in the
    8086 by the execution of an
    instruction.

    At the end of each instruction


    cycle 8086 checks to see if any
    interrupts have been requested.
    • We have two interrupt pins: NMI and INTR
    How does • If we save NMI for power failure interrupt,

    INTR input only INTR is left.

    work? • If the 8086 interrupt flag is set and INTR


    receives a high signal, 8086 will
    (i) Send out 2 interrupt ACK pulses on its
    INTA pin to INTA pin of 8295
    (ii) Multiply the interrupt type it receives
    from the 8259A by 4 to produce an
    address in the interrupt vector table
    (iii) Push the flags on the stack
    (iv) Clear IF and TF
    (v) Push the return address on the stack
    (vi) Get the starting address for the interrupt
    procedure from the interrupt vector
    table and load that address in CS and IP
    (vii) Execute interrupt service.
    Internal block diagram of
    8259A
    • The data bus allows the 8086 to send control words to 8259A
    and read a status word from 8259A. RD and WR control these
    transfer provided CS is low.
    • IR0 to IR7 are eight interrupt pins
    • Any one of these inputs will cause 8259A to assert its INT pin
    high.
    • The INTA input of 8259A is connected with INTA output of 8086
    • 8259A uses the first INTA pulse from 8086 to do some
    activities that depend on the mode in which it is programmed.
    • When it receives the second INTA pulse from 8086, 8295A
    outputs an interrupt type on 8 bit data bus.
    • The interrupt type is determined by IR input and by a number
    set during initialization.
    • The point is 8295 funnels interrupt signals from eight different
    sources into INTR.
    What
    happens if
    interrupt
    signal • Fixed priority mode: simple.

    appears at • IR0 highest and IR7 lowest


    priority
    SAME
    TIME?
    IRR • IMR: Interrupt Mask Registar
    disable(mask) or enable (unmask)
    IMR individual interrupt inputs.

    ISR • IRR: Interrupt Request Register

    priority keeps track of which interrupt inputs


    are asking for service. If an interrupt
    resolver input has an interrupt signal on it the
    the corresponding bit in in the IRR will
    be set.
    • ISR: Interrupt Service Register
    Keeps track of wich interrupt inputs are
    currently being serviced. Corresponding
    bit comes high.
    • Priority resolver: acts as a judge that
    determines if and when an interrupt
    request on one of the IR inputs gets
    serviced.

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