K K Wagh Polytechnic,Nashik

UNIT 4: Microprocessor:8086 and

Modern Microprocessor

CO4: Use 8086 microprocessor environment build

and execute assembly language programs.
(12 marks)
 4.1 Programming model of 8086 assembly language program assembler
directives

BY Ishwari Badhe& Bhoomi Jadhav

Introduction to Microprocessor
•A microprocessor is a multipurpose, clock driven electronic component that is used by computer
• to do it’s work.
•It accepts binary information as input, processes it according to instruction stored in its memory
•and provides results as output.
•It is just like central processing unit(CPU) on a single integrated circuit.
Features of 8086
The most prominent features of a 8086 microprocessor are as follows −
•It has an instruction queue, which is capable of storing six instruction
bytes from the memory resulting in faster processing.
•It was the first 16-bit processor having 16-bit ALU, 16-bit registers,
internal data bus, and 16-bit external data bus resulting in faster
processing.
•It is available in 3 versions based on the frequency of operation −
 8086 → 5MHz
 (c)8086-1 → 10 MHz
•It uses two stages of pipelining, i.e. Fetch Stage and Execute Stage,
which improves performance.
•Fetch stage can prefetch up to 6 bytes of instructions and stores them
in the queue.
•Execute stage executes these instructions.
•It has 256 vectored interrupts.
•It consists of 29,000 transistors.
Comparison between 8085 & 8086 Microprocessor
 Size − 8085 is 8-bit microprocessor, whereas 8086 is 16-bit microprocessor.

 Address Bus − 8085 has 16-bit address bus while 8086 has 20-bit address bus.

 Memory − 8085 can access up to 64Kb, whereas 8086 can access up to 1 Mb of

memory.

 Instruction − 8085 doesn’t have an instruction queue, whereas 8086 has an

instruction queue.

 Pipelining − 8085 doesn’t support a pipelined architecture while 8086 supports a

pipelined architecture.

 I/O − 8085 can address 2^8 = 256 I/O's, whereas 8086 can access 2^16 = 65,536 I/O's.

 Cost − The cost of 8085 is low whereas that of 8086 is high.

Architecture of 8086
The following diagram depicts the architecture
of a 8086 Microprocessor −
4.1Programming model of 8086 assembly language
program assembler directives
(a) The DB directive
(b) The DW directive
(c) The DD directive
(d) The STRUCT (or STRUC) and ENDS directives
(counted as one)
(e)The EQU Directive
(f)The COMMENT directive
(g)ASSUME
(h) EXTERN
(i) GLOBAL
(j) SEGMENT
(k)OFFSET
(l) PROC
(m)GROUP
(n) INCLUDE
Pin diagram of 8086 microprocessor:
Pin diagram of 8086 microprocessor is as
given below:
Intel 8086 is a 16-bit HMOS microprocessor. It
is available in 40 pin DIP chip. It uses a 5V DC
supply for its operation. The 8086 uses a 20-
line address bus. It has a 16-line data bus.
The 20 lines of the address bus operate in
multiplexed mode. The 16-low order address
bus lines have been multiplexed with data
and 4 high-order address bus lines have been
multiplexed with status signals.
AD0-AD15: Address/Data bus. These are low
order address bus. They are multiplexed with
data. When AD lines are used to transmit
memory address the symbol A is used instead
of AD, for example A0-A15. When data are
transmitted over AD lines the symbol D is
used in place of AD, for example D0-D7, D8-
D15 or D0-D15.
A16-A19: High order address bus. These are
S2, S1, S0: Status pins. These pins are active
during T4, T1 and T2 states and is returned to
passive state (1,1,1 during T3 or Tw (when ready is
inactive). These are used by the 8288 bus
controller for generating all the memory and I/O
operation) access control signals. Any change in
S2, S1, S0 during T4 indicates the beginning of a
bus
S2 cycle.
S1 S0 Characteristics
0 0 0 Interrupt acknowledge
0 0 1 Read I/O port
0 1 0 Write I/O port
0 1 1 Halt
1 0 0 Code access
1 0 1 Read memory
1 1 0 Write memory
1 1 1 Passive state
A16/S3, A17/S4, A18/S5, A19/S6 : The specified address lines are multiplexed with
corresponding status signals.
A17/S4 A16/S3 Function
0 0 Extra segment access

0 1 Stack segment access

1 0 Code segment access

1 1 Data segment access

HE’/S7: Bus High Enable/Status. During T1 it is low. It is used to enable

data onto the most significant half of data bus, D8-D15. 8-bit device
connected to upper half of the data bus use BHE (Active Low) signal. It
is multiplexed with status signal S7. S7 signal is available during T2, T3
and T4.
RD’: This is used for read operation. It is an output signal. It is active
when low.
READY : This is the acknowledgement from the memory or slow device
that they have completed the data transfer. The signal made available
by the devices is synchronized by the 8284A clock generator to provide
ready input to the microprocessor. The signal is active high(1).
INTR : Interrupt Request. This is triggered input. This is sampled during the last clock cycles of
each instruction for determining the availability of the request. If any interrupt request is found
pending, the processor enters the interrupt acknowledge cycle. This can be internally masked after
resulting the interrupt enable flag. This signal is active high(1) and has been synchronized
internally.
NMI : Non maskable interrupt. This is an edge triggered input which results in a type II interrupt. A
subroutine is then vectored through an interrupt vector lookup table which is located in the system
memory. NMI is non-maskable internally by software. A transition made from low(0) to high(1)
initiates the interrupt at the end of the current instruction. This input has been synchronized
internally.
INTA : Interrupt acknowledge. It is active low(0) during T2, T3 and Tw of each interrupt
acknowledge cycle.
MN/MX’ : Minimum/Maximum. This pin signal indicates what mode the processor will operate in.
RQ’/GT1′, RQ’/GT0′ : Request/Grant. These pins are used by local bus masters used to force the
microprocessor to release the local bus at the end of the microprocessor’s current bus cycle. Each
of the pin is bi-directional. RQ’/GT0′ have higher priority than RQ’/GT1′.
LOCK’ : Its an active low pin. It indicates that other system bus masters have not been allowed to
gain control of the system bus while LOCK’ is active low(0). The LOCK signal will be active until the
completion of the next instruction.
TEST’ : This examined by a ‘WAIT’ instruction. If the TEST pin goes low(0), execution will continue,
else the processor remains in an idle state. The input is internally synchronized during each of the
clock cycle on leading edge of the clock.
CLK : Clock Input. The clock input provides the basic timing for processing operation and bus control
activity. Its an asymmetric square wave with a 33% duty cycle.
RESET : This pin requires the microprocessor to terminate its present activity immediately. The signal
must be active high(1) for at least four clock cycles.
Vcc : Power Supply( +5V D.C.)
GND : Ground
QS1,QS0 : Queue Status. These signals indicate the status of the internal 8086 instruction queue
according to the table shown below:

QS1 QS0 Status

0 0 No operation

0 1 First byte of op code from queue

1 0 Empty the queue

1 1 Subsequent byte from queue

Flag Registor:The Flag Register in the 8086 microprocessor is a 16-bit register that
contains the current state of the processor. It is divided into two groups: Condition Flags and
Control Flags.
Condition Flags:1. Carry Flag (CF): Set if an arithmetic operation generates a carry or borrow.
2. Parity Flag (PF): Set if the result of an operation has even parity.
3. Auxiliary Carry Flag (AF): Set if an arithmetic operation generates a carry from bit 3 to bit
4. Zero Flag (ZF): Set if the result of an operation is zero.
5. Sign Flag (SF): Set if the result of an operation is negative.
6. Overflow Flag (OF): Set if an arithmetic operation generates an overflow.
Control Flags:1. Trap Flag (TF): Enables or disables single-step mode for debugging.
2. Interrupt Flag (IF): Enables or disables maskable interrupts.
3. Direction Flag (DF): Controls string instruction direction (increment or decrement).
4. Overflow Flag (OF): Also used as a control flag to enable or disable overflow detection.
The Flag Register is accessed using the following instructions:- PUSHF: Pushes the Flag
Register onto the stack.- POPF: Pops the Flag Register from the stack.- LAHF: Loads the AH
register with the Flag Register.- SAHF: Stores the AH register into the Flag Register.
M/IO’: This signal is used to distinguish between memory and I/O operations. The M Signal is Active
high whereas the IO’ Signal is Active Low. When this Pin is High, the memory operations takes place.
On the other hand, when the Pin is low, the Input/Output operations from the peripheral devices
takes place.
=DT/R : Data Transmit/Receive. This pin is required in minimum systems, that want to use an 8286
or 8287 data bus transceiver. The direction of data flow is controlled through the transceiver.
DEN: Data enable. This pin is provided as an output enable for the 8286/8287 in a minimum system
which uses transceiver. DEN is active low(0) during each memory and input-output access and for
INTA cycles.
HOLD/HOLDA: HOLD indicates that another master has been requesting a local bus .This is an
active high(1). The microprocessor receiving the HOLD request will issue HLDA (high) as an
acknowledgement in the middle of a T4 or T1 clock cycle.
ALE : Address Latch Enable. ALE is provided by the microprocessor to latch the address into the
8282 or 8283 address latch. It is an active high(1) pulse during T1 of any bus cycle. ALE signal is
never floated, is always integer.
Data declaration directives:
1. DB – The DB directive is used to declare a BYTE -2-BYTE variable – A BYTE is made up of 8 bits.
Declaration examples:
Byte1 DB 10h
Byte2 DB 255 ; 0FFh, the max. possible for a BYTE
CRLF DB 0Dh, 0Ah, 24h ;Carriage Return, terminator BYTE
2. DW – The DW directive is used to declare a WORD type variable – A WORD occupies 16 bits or (2
BYTE).
Declaration examples:
Word DW 1234h
Word2 DW 65535; 0FFFFh, (the max. possible for a WORD)
3. DD – The DD directive is used to declare a DWORD – A DWORD double word is made up of 32 bits
=2 Word’s or 4 BYTE.
Declaration examples:
Dword1 DW 12345678h
Dword2 DW 4294967295 ;0FFFFFFFFh.
4. STRUCT and ENDS directives to define a structure template for grouping data items.
(1) The STRUCT directive tells the assembler that a user defined uninitialized data structure follows.
The uninitialized data structure consists of a combination of the three supported data types. DB,
DW, and DD. The labels serve as zero-based offsets into the structure. The first element’s offset for
any structure is 0. A structure element is referenced with the base “+” operator before the
element’s name.
A Structure ends by using the ENDS directive meaning END of Structure.
Syntax:
...
...
ENDS
(OR)
STRUC
Structure_element_name element_data_type?
...
...
...
ENDS
DECLARATION:
STRUCT
Byte1 DB?
Byte2 DB?
Word1 DW?
Word2 DW?
Dword1DW?
Dword2 DW?
ENDS
Use OF STRUCT:
The STRUCT directive enables us to change the order of items in the structure when, we reform a file
header and shuffle the data. Shuffle the data items in the file header and reformat the sequence of
data declaration in the STRUCT and off you go. No change in the code we write that processes the file
(5) The EQU Directive
The EQU directive is used to give name to some value or symbol. Each time the
assembler finds the given names in the program, it will replace the name with the
value or a symbol. The value can be in the range 0 through 65535 and it can be
another Equate declared anywhere above or below.
The following operators can also be used to declare an Equate:
THIS BYTE
THIS WORD
THIS DWORD
A variable – declared with a DB, DW, or DD directive – has an address and has space
reserved at that address for it in the .COM file. But an Equate does not have an
address or space reserved for it in the .COM file.
Example:
A – Byte EQU THIS BYTE
DB 10
A_ word EQU THIS WORD
DW 1000
A_ dword EQU THIS DWORD
DD 4294967295
Buffer Size EQU 1024
Buffer DB 1024 DUP (0)
Buffed_ ptr EQU $ ; actually points to the next byte after the; 1024th byte in buffer.
(6) Extern:
It is used to tell the assembler that the name or label following the directive are I some other
assembly module. For example: if you call a procedure which is in program module assembled at a
different time from that which contains the CALL instructions ,you must tell the assembler that the
procedure is external the assembler will put information in the object code file so that the linker can
connect the two module together.
Example:
PROCEDURE -HERE SEGMENT
EXTERN SMART-DIVIDE: FAR ; found in the segment; PROCEDURES-HERE
PROCEDURES-HERE ENDS
(7) GLOBAL:
The GLOBAL directive can be used in place of PUBLIC directive .for a name defined in the current
assembly module; the GLOBAL directive is used to make the symbol available to the other modules.
Example:
GLOBAL DIVISOR:
WORD tells the assembler that DIVISOR is a variable of type of word which is in another assembly
module or EXTERN.
(8) SEGMENT:
It is used to indicate the start of a logical segment. It is the name given to the the segment. Example:
the code segment is used to indicate to the assembler the start of logical segment.
(9) PROC: (PROCEDURE)
It is used to identify the start of a procedure. It follows a name we give the procedure.
After the procedure the term NEAR and FAR is used to specify the procedure Example: SMART-DIVIDE
PROC FAR identifies the start of procedure named SMART-DIVIDE and tells the assembler that the
(11) INCLUDE:
It is used to tell the assembler to insert a block of source code from the named file into
the current source module. This shortens the source module. An alternative is use of
editor block command to cop the file into the current source module.
(12) OFFSET:
It is an operator which tells the assembler to determine the offset or displacement of a
named data item from the start of the segment which contains it. It is used to load the
offset of a variable into a register so that variable can be accessed with one of the
addressed modes. Example: when the assembler read MOV BX.OFFSET PRICES, it will
determine the offset of the prices.
(13) GROUP:
It can be used to tell the assembler to group the logical segments named after the
directive into one logical group. This allows the contents of all he segments to be
accessed from the same group. Example: SMALL-SYSTEM GROUP CODE, DATA, STACK-SEG.
Thank you