A closed form expression for minimum operating voltage of cmos d flip-flop

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A Closed-Form Expression for Minimum Operating Voltage of CMOS D
Flip-Flop
Abstract:
In this paper, a closed-form expression for estimating the minimum operating voltage
(VDDmin) of D flip-flops (FFs) is proposed. VDDmin is defined as the minimum supply
voltage at which the FFs are functional without errors. The proposed expression indicates
that VDDmin of FFs is a linear function of the square root of logarithm of the number of
FFs, and its slope depends on the within-die variation of the threshold voltage (VTH) and
its intercept depends on the balance between PMOS and NMOS, which is mainly due to
the die-to-die VTH variation. The proposed expression of VDDmin is validated by the
simulation results as well as the silicon measurements. Finally, we discuss the
dependence of VDDmin on the device parameters..
Software Implementation:
 TANNER EDA
Existing System:
ENERGY efficient computing is becoming increasingly important in the Internet of
Things era. The near/sub threshold operation is one of the most promising approaches to
maximize the energy efficiency. Fig. 1(a) shows the energy as a function of the supply
voltage (VDD). As VDD is reduced to the near/sub threshold region, the energy
decreases and is minimized at VDD = VOPT, since lowering VDD reduces the dynamic
energy, whereas it significantly raises the leakage energy due to an exponential increase
of the circuit delay threshold region.

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This is considered the target voltage for maximizing the energy efficiency. One of the
concerns to achieve the target voltage is the minimum operating voltage (VDDmin).
VDDmin is defined as the minimum VDD at which a circuit is functional without errors.
If VDDmin is higher than VOPT, minimum energy cannot be achieved, as shown in Fig.
1(a). Therefore, VDDmin is an indispensable factor for the near/sub threshold circuit
design. The ideal VDDmin of a single CMOS inverter was derived in and it was found to
be 36 mV at 300 K. Taking the manufacturing variability into consideration, however,
VDDmin is much higher in actual implementation. For example, Niiyama et al measured
VDDmin of ring oscillators and reported that VDDmin is more than 100 mV. They also
demonstrated that VDDmin depends on the number of inverters.

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Such a dependence was analytically investigated, which howed that VDDmin is a linear
function of the square root of logarithm of the number of logic gates. Furthermore, its
slope depends on the within-die (WID) variation of threshold voltage (VTH) and its
intercept depends on the balance between NMOS and PMOS, which is mainly due to the
die-to-die (D2D) VTH variation, as shown in Fig. 1(b). This means that VDDmin
becomes a concern especially in large-scale integrated circuits.
Fig. 1. (a) Energy of CMOS logic circuit. (b) Dependence of VDD min on the number of logic gates.
However, the analytical investigations on VDDmin focus only on combinational logic
gates, such as inverters and NAND gates, whereas D flip-flops (FFs) are not considered.
Although VDDmin of FFs was measured, the factors that influence VDDmin have not
been clarified yet. Since FFs are an important component in a logic circuit, analytical
investigations on VDDmin of FFs are also essential. In this paper, a closed-form
expression of VDDmin of FFs is proposed.

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This paper is the first work to show that the dependence of VDDmin of FFs on the
number of gates is same as that of combinational logic circuits presented. The
contributions of this paper are as follows. 1) Conventionally, Monte Carlo simulations,
which usually take a large computational time, are required to obtain VDDmin of FFs.
Using the proposed closed-form expression, VDDmin of the FF can be estimated easily.
2) The proposed expression shows what kind of and how the device parameters
determine VDDmin. Accordingly, circuit designers can identify better process
technologies and understand how FFs should be designed in terms of reducing VDDmin.
Disadvantages:
 Less Efficiency
 Advanced technology is not used
 Maximizing the circuit energy.
Proposed System:
Determination Factor of VDDmin
In this paper, VDDmin is defined as the minimum VDD at which FFs work without
functional errors. It should be noted that the setup and hold errors are not considered as
functional errors in this paper, since they have already been well investigated and can be
avoided via circuit design. On the other hand, the determination factor of VDDmin is
unknown. Therefore, we assume that VDDmin is determined not by the dynamic
behavior induced by the clock signal transition but by the static characteristics of the
master and slave latches in the FF and the FF fails when the hold static noise margin
(SNM) of the cross-coupled pair in either the master or the slave latch is insufficient.

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Usually, SNM is used for evaluating the stability of an Static Random Access Memory
cell. In this paper, we exploit the SNM as a metric for judging whether the FF is
functional. Fig. 2 shows the circuit schematic of a master latch of the FF assumed in this
paper. When the clock signal is high, two tri state inverters are considered as an
equivalent inverter, which is denoted by TINV, as shown in Fig. 2. In this case, the
master latch forms a cross-coupled pair consisting of an inverter, which is denoted by
INV, and TINV. In this section, we focus on the SNM of this cross-coupled pair.
Fig. 2. Circuit schematic of a master latch of an FF.

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the characteristics of TINV depend on the voltage of the input (D in Fig. 2). However, the
dependence of the characteristics on D is relatively small; hence, it is not considered in
the derivation described in this section for simplicity.
To obtain results that are more accurate, the dependence should be taken into account. In
addition, the characteristics of TINV may not perfect. In this case, the I–V characteristics
of TINV should be approximated where VGS is close to VDD. The simulations
conducted in this paper are based on the 32-nm-predictive technology model (PTM)
CMOS technology.
Advantages:
 More Efficiency
 32-nm Cmos technology is used
 Minimizing the circuit energy
References:
[1] S. Paul et al., “An energy harvesting wireless sensor node for IoT systems featuring a near-threshold
voltage IA-32 microcontroller in 14 nm tri-gate CMOS,” in Symp. VLSI Circuits Dig. Tech. Papers,
2016, pp. 78–79.
[2] J. Myers, A. Savanth, D. Howard, R. Gaddh, P. Prabhat, and D. Flynn, “An 80 nW retention
11.7pJ/cycle active sub threshold ARM cortexM0+ subsystem in 65 nm CMOS for WSN applications,”
in ISSCC Dig. Tech. Papers, 2015, pp. 134–145.
[3] H. Kaul et al., “A 320 mV 56 μW 411 GOPS/watt ultra-low voltage motion estimation accelerator in
65 nm CMOS,” IEEE J. Solid-State Circuits, vol. 44, no. 1, pp. 107–114, Jan. 2009.

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[4] H. Fuketa et al., “Device-circuit interactions in extremely low voltage CMOS designs,” in IEDM
Tech. Dig., 2011, pp. 559–562.
[5] H. Fuketa et al., “A closed-form expression for estimating minimum operating voltage (VDDmin) of
CMOS logic gates,” in Proc. DAC, 2011, pp. 984–989.
[6] J. Meindl and J. Davis, “The fundamental limit on binary switching energy for tera scale integration
(TSI),” IEEE J. Solid-State Circuits, vol. 35, no. 10, pp. 1515–1516, Oct. 2000. This article has been
accepted for inclusion in a future issue of this journal. Content is final as presented, with the exception
of pagination. 10 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI)
SYSTEMS
[7] M. Alioto, “Understanding DC behavior of sub threshold CMOS logic through closed-form
analysis,” IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 57, no. 7, pp. 1597–1607, Jul. 2010.
[8] T. Niiyama, Z. Piao, K. Ishida, M. Murakata, M. Takamiya, and T. Sakurai, “Increasing minimum
operating voltage (VDDmin) with number of CMOS logic gates and experimental verification with up to
1Mega-stage ring oscillators,” in Proc. ISLPED, 2008, pp. 117–122.
[9] T. Yasufuku et al., “24% power reduction by post-fabrication dual supply voltage control of 64
voltage domains in VDDmin limited ultra low voltage logic circuits,” in Proc. ISQED, 2012, pp. 586–
591.
[10] H. Fuketa et al., “12.7-times energy efficiency increase of 16-bit integer unit by power supply
voltage (VDD) scaling from 1.2V to 310 mV enabled by contention-less flip-flops (CLFF) and separated
VDD between flip-flops and combinational logics,” in Proc. ISLPED, 2011, pp. 21–26.
[11] H. Fuketa et al., “Minimizing energy of integer unit by higher voltage flip-flop: VDDmin-aware
dual supply voltage technique,” IEEE Trans. VLSI Syst., vol. 21, no. 6, pp. 1175–1179, Jun. 2013.
[12] J. Tolbert, X. Zhao, S. Lim, and S. Mukhopadhyay, “Slew-aware clock tree design for reliable sub
threshold circuits,” in Proc. ISLPED, 2009, pp. 15–20.
[13] A. J. Bhavnagarwala, X. Tang, and J. D. Meindl, “The impact of intrinsic device fluctuations on
CMOS SRAM cell stability,” IEEE J. Solid-State Circuits, vol. 36, no. 4, pp. 658–665, Apr. 2001. [14]
H. Fuketa, S. O’Uchi, K. Fukuda, T. Mori, Y. M

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