Synthesis & gate-level simulation is introduced. The key topics covered include basic concepts of logic synthesis using Design Compiler, including logic level optimization, mapping, boundary optimization, and static timing analysis. Simulation of the gate-level netlist generated after synthesis is also discussed. An example lab is outlined to synthesize a simple 8-bit microprocessor and simulate the gate-level netlist.
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More Related Content
design-compiler.pdf
1. Synthesis &
Synthesis & Gate
Gate-
-Level
Level
Simulation
Simulation
REF:
• CIC Training Manual – Logic Synthesis with Design Compiler, July, 2006
• TSMC 0.18um Process 1.8-Volt SAGE-XTM Stand Cell Library Databook, September, 2003
• TPZ973G TSMC 0.18um Standard I/O Library Databook, Version 240a, December 10, 2003
9 3G S C 0 8u Sta da d /O b a y ataboo , e s o 0a, ece be 0, 003
• Artisan User Manual
Advanced Reliable
Systems (ARES) Lab.
1
3. Outline
Basic Concept of the Synthesis
Synthesis Using Design Compiler
Synthesis Using Design Compiler
Simulation-Based Power Estimation Using PrimePower
Artisan Memory Compiler
y p
LAB
Advanced Reliable Systems (ARES) Lab. 3
4. Basic Concept of the Synthesis
Basic Concept of the Synthesis
Advanced Reliable Systems (ARES) Lab. 4
5. Cell-Based Design Flow
MATLAB/ C/ C++/ System C/
ADS/ Covergen (MaxSim)
Memory Generator
Spec.
System Level
ADS/ Covergen (MaxSim)
NC-Verilog/ ModelSim
Debussy (Verdi)/ VCS
Verilog/ VHDL Syntest
RTL Level
Design/ Power Compiler
DFT Compiler/ TetraMAX
mpiler/
Fusion
Conformal/
Formality
Logic Synthesis
Design for Test
NC-Verilog/ ModelSim
Debussy (Verdi)/ VCS
hysical
Com
gma
Blast
Gate Level
SOC Encounter/ Astro
DRC/ LVS (Calibre)
Ph
Mag
GDS II
Layout Level
Post-Layout
Verification
PVS: Calibre xRC/ NanoSim
(Time/ Power Mill)
Verification
Advanced Reliable Systems (ARES) Lab.
Tape Out
5
6. What is Synthesis
Synthesis = translation + optimization + mapping
if(high_bits == 2’b10)begin
residue = state table[i];
_ [ ];
end
else begin
residue = 16’h0000;
end Translate (HDL Compiler)
HDL Source
HDL Source
(RTL)
Optimize + Mapping
(HDL Compiler)
No Timing Info.
(HDL Compiler)
Generic Boolean
(GTECT)
Timing Info.
The synthesis is constraint driven
Advanced Reliable Systems (ARES) Lab.
Target Technology
and technology independent !!
6
7. Logic Synthesis Overview
RTL Design
HDL Design Ware
DW
Architecture
Compiler
Design Ware
Library
Developer
Optimization
Design
Compiler
Technology
Lib
Compiler
Logic
Optimization Compiler Library
p
Optimized
Optimization
Optimized
Gate-Level Netlist
Advanced Reliable Systems (ARES) Lab. 7
8. Compile
RTL code
or netlist
Optimized Design (Gate-Level Netlist)
Compile
Attributes &
Constraints
Schematic
Reports (Timing, Area, Power, …, etc)
Constraints Reports
Flatten
Technology
Lib
Structure
( g, , , , )
Logic Level Optimization
Library
(Can be set by the GUI
interface or user-defined
Script File !!)
Gate Level Optimization
Map
Technology
Library
Advanced Reliable Systems (ARES) Lab.
Library
8
9. Logic Level Optimization
Operate with Boolean representation of a circuit
Has a global effect on the overall area/speed
Has a global effect on the overall area/speed
characteristic of a design
Strategy
Strategy
Structure
Flatten (default OFF)
( )
If both are true, the design is “first flattened and then structured”
Ex:
f = acd + bcd +e
g = ae’ + be’
h = cde
f = xy + e
g = xe’
h = ye
f0 = at
f1 = d + t
f2 = t’e
f0 = ab + ac
f1 = b + c + d
f2 = b’c’e
h cde h ye
x = a + b
y = cd
(Structure)
f2 t e
t = b + c
f2 b c e
(Flatten)
Advanced Reliable Systems (ARES) Lab. 9
10. Gate Level Optimization - Mapping
Combinational Mapping
Mapping rearranges components combining and re-combining
Mapping rearranges components, combining and re-combining
logic into different components
May use different algorithms such as cloning, resizing, or
b ff i
buffering
Try to meet the design rule constraints and the timing/area goals
Sequential Mapping
Sequential Mapping
Optimize the mapping to sequential cells technology library
Analyze combinational logics surrounding a sequential cell to see
y g g q
if it can absorb the logic attribute with HDL
Try to save speed and area by using a more complex sequential
cells
cells
Advanced Reliable Systems (ARES) Lab. 10
11. Mapping
Combinational Mapping Sequential Mapping
a
a
a
b
a
b
c c
A
B D Q
AND_FF
Q
A
B
a
b
a
b
c c
a a c
c
x1 x1 x2 x4
D Q
A Q
A
B
Critical Path Critical Path
D Q
A
B
Loop_FF
Q
B
a f
g a
f
g
(assume g loading high)
Advanced Reliable Systems (ARES) Lab.
g
11
12. Boundary Optimization
Design Compiler can do some optimizations across boundaries
1. Removes logic driving unconnected output ports
2. Removes redundant inverters across boundaries
3. Propagates constants to reduce logic
Advanced Reliable Systems (ARES) Lab. 12
13. Static Timing Analysis
Main steps of STA
Break the design into sets of timing paths
Break the design into sets of timing paths
Calculate the delay of each path
Check all path delays to see if the given timing constraints are
met
Four types of paths
( )
Register - Register (Reg - Reg)
Primary Input - Register (PI - Reg)
Register - Primary Output (Reg - PO)
Register - Primary Output (Reg - PO)
Primary Input - Primary Output (PI - PO)
Advanced Reliable Systems (ARES) Lab. 13
14. Static Timing Analysis (Cont’)
To meet the setup time requirement:
Trequire >= Tarrival
- Setup Time
(T l k > 0 denotes
require arrival
Reg to Reg
Tarrival = Tclk1 + TDFF1(clk->Q) + TPATH
T T T
(Tslack > 0 denotes
“no timing violation”)
Trequire = Tclk2 - TDFF2(setup)
Tslack = Trequire - Tarrival
Clk_source
clk1
clk1
TDFF1 + Tpath
Tarrival
D Q
DFF1
D Q
DFF2
PATH
Tarrival
data
clk2
Trequire
Tsetup
Tslack
Q
clk1 Q
clk2
Advanced Reliable Systems (ARES) Lab. 14
15. Static Timing Analysis (Cont’)
PI to Reg
Tarrival = TPI(delay) + TPATH
T T T
- Setup Time
Trequire = Tclk1 - TDFF1(setup)
Tslack = Trequire - Tarrival
Clk_source
Tarrival
Tpath
D Q
DFF1
PATH
TPI(delay)
T
PI data
clk1
Trequire
Tslack
D Q
Q
clk1
Tsetup
Tarrival
Advanced Reliable Systems (ARES) Lab. 15
16. Static Timing Analysis (Cont’)
Reg to PO
Tarrival = Tclk1 + TDFF1(clk->Q) + TPATH
T T T
- Setup Time
Trequire = Tcycle - TPO(output delay)
Tslack = Trequire - Tarrival
Clk_source
clk1
clk1
TDFF1 + Tpath
T
D Q
DFF1
PATH
T
PO data
Tarrival
Trequire Tslack
D Q
Q
clk1
TPO(output delay)
Tarrival
Advanced Reliable Systems (ARES) Lab.
Tslack
16
17. Static Timing Analysis (Cont’)
PI to PO
Tarrival = TPI(delay) + TPATH
T = T - T
- Setup Time
Trequire = Tcycle - TPO(output delay)
Tslack = Trequire - Tarrival
Clk_source
TPI + Tpath
Tarrival
PATH
T
PO
PI data
Trequire Tslack
TPO(output delay)
Tarrival
Advanced Reliable Systems (ARES) Lab.
Tslack
17
18. Static Timing Analysis (Cont’)
To meet the hold time requirement:
Trequire <= Tarrival
- Hold Time
require arrival
Reg to Reg
Tarrival = Tclk1 + TDFF1(clk->Q) + TPATH
T T + T
Trequire = Tclk2 + TDFF2(hold)
Tslack = Tarrival - Trequire
Clk source
Clk_source
clk1
TDFF1 + Tpath
clk2
D Q
DFF1
D Q
DFF2
PATH
Tarrival
data 1
data 0
clk2
T i l
Trequire
Thold
Tslack
Q
clk1 Q
clk2
Advanced Reliable Systems (ARES) Lab.
Tarrival
18
19. Static Timing Analysis (Cont’)
PI to Reg
Tarrival = TPI(delay) + TPATH
- Hold Time
Trequire = Tclk1 + TDFF(hold)
Tslack = Tarrival - Trequire
Reg to PO
g
Tarrival = Tclk1 + TDFF(clk->Q) + TPATH
Trequire = - TPO(output delay)
T l k = T i l - T i
Tslack Tarrival Trequire
PI to PO
Tarrival = TPI(delay) + TPATH
T T
Trequire = - TPO(output delay)
Tslack = Tarrival - Trequire
Advanced Reliable Systems (ARES) Lab. 19
22. Notice Before Synthesis
Your RTL design
Area
Cycle
Better
Functional verification by some high-level language
Also, the code coverage of your test benches should be verified (i.e. VN)
Coding style checking (i.e. n-Lint)
Time
Coding style checking (i.e. n Lint)
Good coding style will reduce most hazards while synthesis
Better optimization process results in better circuit performance
E d b i f h i
Easy debugging after synthesis
Constraints
The area and timing of your circuit are mainly determined by your
The area and timing of your circuit are mainly determined by your
circuit architecture and coding style
There is always a trade-off between the circuit timing and area
In fact, a super tight timing constraint may be worked while synthesis,
but failed in the Place & Route (P&R) procedure
Advanced Reliable Systems (ARES) Lab. 22
23. Synthesis Using Design Compiler
Synthesis Using Design Compiler
Advanced Reliable Systems (ARES) Lab. 23
24. <.synopsys_dc.setup> File
Create individual synopsys setup file for each folder
link_library : the library used for interpreting input description
Any cells instantiated in your HDL code
y y
Wire load or operating condition modules used during synthesis
target_library : the ASIC technology which the design is mapped
f
symbol_library : used for schematic generation
search_path : the path for unsolved reference library
synthetic path : designware library
synthetic_path : designware library
Advanced Reliable Systems (ARES) Lab. 24
25. <.synopsys_dc.setup> File (Cont’)
MEMs libraries are also included in this file
Ex:
MEM Libraries (.db file)
Note that the MEM DB files are converted from
the LIB files which are generated from the Artisan !!
(.synopsys_dc.setup File)
the LIB files which are generated from the Artisan !!
Advanced Reliable Systems (ARES) Lab. 25
26. Hard Macro
Memory block
Memory library files (synopsys model) are generated by memory
il
compiler
Translate library files (.lib) to db files (.db) for synthesis
Four corners: fast@-40C fast@0C typical and slow
Four corners: fast@ 40C, fast@0C, typical, and slow
Memory block
Advanced Reliable Systems (ARES) Lab. 26
27. Settings for Using Memory
Convert *.lib to *.db
> dc shell
any memory LIB file
> dc_shell
dc_shell-t> read_lib t13spsram512x32_slow_syn.lib
dc_shell-t> write_lib t13spsram512x32 -output
t13spsram512x32_slow_syn.db
Modify <.synopsys_dc.setup> File:
“*
user library name, which should
be the same as the library name
in the Artisan
set link_library “* slow.db t13spsram512x32_slow.db
dw_foundation.sldb”
set target library “slow db t13spsram512x32 slow db”
memory DB file add to the file
set target_library slow.db t13spsram512x32_slow.db
Before the synthesis, the memory HDL model should be
blocked in your netlist
y
Advanced Reliable Systems (ARES) Lab. 27
28. Test Pins Reservation
You can add the floating test pins to your design before synthesis
se: scan enable
si: scan input
so: scan output
scantest: control signal for memory shadow wrapper (i e memory is used)
scantest: control signal for memory shadow wrapper (i.e. memory is used)
Ex:
Normal IO Declaration
Test IO Declaration
The pins will be connected to scans after the scan chain insertion
Advanced Reliable Systems (ARES) Lab.
p
28
29. CHIP-Level Netlist
The CHIP-level netlist consists of your Core-level netlist and the
PADs
E CHIPv
CORE
CORNER2
CORNER1
Ex: CHIP.v
CORE.v
(CHIP-Level Declaration)
CORE
I_CLK
CLK
CORNER3 CORNER4
O_CSO
CSO
CORNER3 CORNER4
(CORE-Level Design)
(Input PAD) I_CLK CLK
PAD C
(Output PAD) CSO O_CSO
I PAD
(IO PAD D l ti )
Advanced Reliable Systems (ARES) Lab.
(Output PAD) (IO PAD Declaration)
29
30. How To Choose the IO PAD
You can reference the Databook of the IO PAD in CIC Design Kit
Generally, the “PDIDGZ” is used as the input PAD
Trade-off when considering
the output PAD
High driving SSN
Ex:
High driving SSN
Low driving Delay
Note that the loading of the
Note that the loading of the
CIC tester is 40pf
[REF: TPZ973G TSMC 0.18um Standard
I/O Library Databook, Version 240a,
December 10, 2003]
Advanced Reliable Systems (ARES) Lab.
December 10, 2003]
30
32. Getting Started
Prepare Files:
*.v files
*.db files (i.e. memory is used)
S h i i fil (i d ib d l )
Synthesis script file (i.e. described later)
linux %> dv
Tool Bar
Logic Hierarchy
Vi
View
Log Window
(GUI view of the Design Vision)
Command Line
Advanced Reliable Systems (ARES) Lab. 32
33. Read File Design Import
Read netlists or other design descriptions into Design Compiler
File/Read
Supported formats
Verilog: .v
VHDL: .vhd
System Verilog: .sv
EDIF
PLA (Berkeley Espresso): .pla
Synopsys internal formats:
DB (binary): db
DB (binary): .db
Enhance db file: .ddc
Equation: .eqn
State table: st
State table: .st
read_file -format verilog file name.v (“/usr/LAB_DV/syn/cpu.v”)
read file -format ddc file name.ddc
{ Command Line }
Advanced Reliable Systems (ARES) Lab.
read_file format ddc file name.ddc
33
34. PAD Parameters Extraction
Input PAD
Input delay
p y
Input driving
Output PAD
O t t d l
Output delay
Output loading
CHIPv
CORE.v
(delay, loading)
(delay, driving) (chip_const.tcl)
{ Command Line }
CHIP.v
current_design CHIP
characterize [get_cells CORE]
current_design CORE
write script -format dctcl -o chip const.tcl
Advanced Reliable Systems (ARES) Lab.
write_script format dctcl o chip_const.tcl
34
35. Uniquify
Select the most top design of the hierarchy
Hierarchy/Uniquify/Hierarchy
uniquify
{ Command Line }
(Design View) (Log Window)
Advanced Reliable Systems (ARES) Lab.
uniquify
35
36. Design Environment Setting Design
Environment
Setting Operating Environment
Setting Don’t Used Cells
Setting Don t Used Cells
Setting Input Driving Strength
Setting Output Loading
Setting Output Loading
Setting Input/Output Delay
Setting Wire Load Model
Setting Wire Load Model
Advanced Reliable Systems (ARES) Lab. 36
37. Setting Operating Condition
Attributes/Operating Environment/Operating Conditions
Setup/Hold time is evaluated
set_operating_conditions -max “slow” -max_library “slow” -min “fast”
-min library “fast”
{ Command Line }
Advanced Reliable Systems (ARES) Lab.
min_library fast
37
38. Setting Don’t Used Cells
Some standard cells are for special purposes
Buffering clock
Buffering clock
CLKBUF*
Inverting clock
CLKINV*
Creating delay (delay cell)
Tie cells
Tie cells
TIE*
DFT cells
SDF* and SEDF*
{ Command Line }
set_dont_use slow/CLKBUF*
set_dont_use typical/CLKBUF*
set_dont_use fast/CLKBUF*
{ Command Line }
Advanced Reliable Systems (ARES) Lab. 38
39. Setting Drive Strength/Input Delay for PADs
Assume that we use the input PAD “PDIDGZ”
my design
PAD C
FF
Q
D
b
Input PAD
(PDIDGZ)
(PDIDGZ)
set_drive [expr 0.288001] [all_inputs]
set input delay [expr 0.34] [all inputs]
{ Command Line }
Advanced Reliable Systems (ARES) Lab.
_ p _ y [ p ] [ _ p ]
39
40. Setting Load/Output Delay for PADs
Assume that we use the output PAD “PDO24CDG”
my design
FF
Q
D d
clk
Output PAD PAD
I
(PDO24CDG)
clk
OEN
(PDO24CDG)
{ Command Line }
set_load [expr 0.06132] [all_outputs]
set_output_delay [expr 2] [all_outputs]
Advanced Reliable Systems (ARES) Lab. 40
41. Setting Wire Load Model
Attributes/Operating Environment/Wire Load
Recommend
(Worst Case)
set_wire_load_model -name “tsmc18_wl10” -library “slow”
set wire lode mode “top”
{ Command Line }
Advanced Reliable Systems (ARES) Lab.
set_wire_lode_mode top
41
43. Sequential Circuit Specify Clock
Select the “clk” pin on the symbol
Attributes/Specify Clock
set fix hold: respect the hold time
set_fix_hold: respect the hold time
requirement of all clocked flip-flops
set_dont_touch_network: do not re-buffer
th l k t k
{ Command Line }
the clock network
set sys_clk clk1
creat_clock -name $sys_clk -period 10 $sys_clk
set_dont_touch_network $sys_clk
t fi h ld $ lk
{ Command Line }
Advanced Reliable Systems (ARES) Lab.
set_fix_hold $sys_clk
43
44. Setting Clock Skew
Different clock arrival time
Ex:
FF
clk
FF
FF
FF
experience
Small circuit: 0.3 ns
Large circuit: 0 5 ns (Ti i R t)
set_clock_uncertainty -setup 0.6 $sys_clk
set clock uncertainty -hold 0.5 $sys clk
{ Command Line }
Large circuit: 0.5 ns (Timing Report)
Advanced Reliable Systems (ARES) Lab.
set_clock_uncertainty hold 0.5 $sys_clk
44
45. Setting Clock Latency
Source latency is the propagation time from the actual clock origin to
the clock definition point in the design
This setting can be avoid if the design is without the clock generator
Ex:
Your Design
Origin of Clock
Source Latency
3ns
experience
Small circuit: 1 ns
Large circuit: 3 ns
Source Latency
set clock latency 1 [get clocks clk]
{ Command Line }
Large circuit: 3 ns
Advanced Reliable Systems (ARES) Lab.
set_clock_latency 1 [get_clocks clk]
45
46. Setting Ideal Clock
Since we usually let the clock tree synthesis (CTS)
procedure performed in the P&R (i e
procedure performed in the P&R (i.e.
set_dont_touch_network), the clock source driving
capability is poor
Thus, we can set the clock tree as an ideal network
without driving issues
Avoid the hazard in the timing evaluation
set ideal network [get clocks clk]
{ Command Line }
Advanced Reliable Systems (ARES) Lab.
set_ideal_network [get_clocks clk]
46
47. Setting Don’t Touch Macro
Modules have been synthesized/optimized
S t d t t h t id ti i th ith
Set dont_touch to avoid optimize the macro with
other modules
Synthesized
core
core
set dont touch module name
{ Command Line }
Advanced Reliable Systems (ARES) Lab. 47
set_dont_touch module_name
49. Combination Circuit – Maximum Delay
Constraints
For combinational circuits primarily (i.e. design with no clock)
Select the start & end points of the timing path
Attributes/Optimization Constraints/Timing Constraints
Attributes/Optimization Constraints/Timing Constraints
Ex:
Maximum
Maximum
Delay
Constraint
(5ns = 200 MHz)
Minimum
Delay
Delay
Constraint
Advanced Reliable Systems (ARES) Lab. 49
51. Setting Area/Fanout Constraint
Attributes/Optimization
Constraints/Design
Constraints
If you only concern the circuit
area but don’t care about the
area, but don t care about the
timing
You can set the max area
constraints to 0
constraints to 0
set_max_area 0
set max fanout 32 [get designs CORE]
{ Command Line }
Advanced Reliable Systems (ARES) Lab.
set_max_fanout 32 [get_designs CORE]
51
52. Compile the Design Compile the
Design
Design/Compile Design
compile -map_effort high -boundary_optimization
compile ultra -no autoungroup (time consuming)
{ Command Line }
Advanced Reliable Systems (ARES) Lab.
compile_ultra -no_autoungroup (time consuming)
52
53. Example for DFT Insertion DFT Insertion
####DB mode####
set_dft_configuration -autofix
set dft configuration -shadow wrapper
DB
Mode
{ Command Line }
set_dft_configuration shadow_wrapper
set_scan_configuration -style multiplexed_flip_flop
set_scan_configuration -clock_mixing no_mix
set_scan_configuration -methodology full_scan
set scan signal test scan in -port si
Mode
set_scan_signal test_scan_in port si
set_scan_signal test_scan_out -port so
set_scan_signal test_scan_enable -port se
set_dft_signal test_mode -port scantest
set test hold 0 rst
set_test_hold 0 rst
set_test_hold 1 scantest
set_test_hold 1 se
create_test_clock -period 100 -waveform [list 40 60] [find port "clk"]
set port configuration -cell RA1SHD256x8 -clock clk
set_port_configuration cell RA1SHD256x8 clock clk
set_port_configuration -cell RA1SHD256x8 -port "Q" -tristate -read {"OEN" 0} -clock clk
set_port_configuration -cell RA1SHD256x8 -port "A" -write {"WEN" 0} -clock clk
set_port_configuration -cell RA1SHD256x8 -port "D" -write {"WEN" 0} -clock clk
set wrapper element RA1SHD256x8 -type shadow
set_ appe _e e e t S 56 8 type s ado
set_wrapper_element FJU_MEM -type shadow
set_fix_multiple_port_nets -all -constants -buffer_constants [get_designs *]
insert_dft
Advanced Reliable Systems (ARES) Lab. 53
54. Example for DFT Insertion (Cont’)
####XG mode####
create_port –dir in scan_in XG
Mode
{ Command Line }
create_port –dir out scan_out
create_port –dir in scan_en
compile –scan –boundary_optimization
set scan configuration –internal clocks single –chain count 1 –clock mixing no mix
Mode
set_scan_configuration –internal_clocks single –chain_count 1 –clock_mixing no_mix
set_dft_signal –view exist –type TestClock –timing {45 55} –port {clk}
set_dft_signal –view exist –type Reset –active 1 –port reset
set_dft_signal –view spec –type ScanEnable –port scan_en –active 1
g y
set_dft_signal –view spec –type ScanDataIn –port scan_in
set_dft_signal –view spec –type ScanDataOut –port scan_out
set_scan_path chain1 –view spec –scan_data_in scan_in –scan_data_out scan_out
create_test_protocol
dft_drc
preview_dft –show scan_clocks
set false path –from [get ports scan en]
set_false_path –from [get_ports scan_en]
insert_dft
Advanced Reliable Systems (ARES) Lab. 54
55. Compile After DFT Compile After
DFT
compile -scan
check_scan
{ Command Line }
report_test -scan_path
estimate_test_coverage
The fault coverage will be shown as below:
The fault coverage will be shown as below:
Advanced Reliable Systems (ARES) Lab. 55
57. Floating Port Removing
Due to some ports in the standard cells are not used in
your design
your design
remove_unconnected_ports -blast_buses [get_cells -hierarchical *]
{ Command Line }
Advanced Reliable Systems (ARES) Lab. 57
58. Chang Naming Rule Script Naming Rule
Changing
Purpose: Let the naming-rule definitions in the gate-level netlist are
the same as in the timing file (e.g. *.sdf file)
Also, the wrong naming rules may cause problems in the LVS
{ Command Line }
set bus_inference_style {%s[%d]}
set bus_naming_style {%s[%d]}
set hdlout_internal_busses true
{ Command Line }
change_names -hierarchy -rule verilog
define_name_rules name_rule -allowed "A-Z a-z 0-9 _" -max_length 255 -type cell
define_name_rules name_rule -allowed "A-Z a-z 0-9 _[]" -max_length 255 -type net
define name rules name rule -map {{"*cell*""cell"}}
define_name_rules name_rule -map {{ cell cell }}
define_name_rules name_rule -case_insensitive
change_names -hierarchy -rules name_rule
Advanced Reliable Systems (ARES) Lab. 58
59. Save Design Save Design
Five design files:
*.spf: test protocol file for ATPG tools (i.e. TetraMax)
*.sdc: timing constraint file for P&R
*.vg: gate-level netlist for P&R
* sdf: timing file for Verilog simulation
.sdf: timing file for Verilog simulation
*.ddc: binary file (i.e. all the constraints and synthesis results are
recorded)
{ C d Li }
REPORT WORK syn tbench script
write -f ddc -o [format "%s%s" [format "%s%s" "../WORK/" $TOP_BLOCK] ".ddc"] -
no_implicit -hier
write -f verilog -o [format "%s%s" [format "%s%s" "../WORK/" $TOP_BLOCK] “_syn.v"] -
{ Command Line }
g [ [ _ ] _ y ]
no_implicit -hier
write_sdc [format "%s%s" [format "%s%s" "../WORK/" $TOP_BLOCK] ".sdc"]
write_sdf -version 2.1 -context verilog [format "%s%s" [format "%s%s" "../WORK/"
$TOP BLOCK] “ sdf“]
Advanced Reliable Systems (ARES) Lab.
$TOP_BLOCK] .sdf ]
59
61. Report Design Hierarchy
Hierarchy report shows the component used in your each block & its
hierarchy
Design/Report Design Hierarchy
Ex:
Advanced Reliable Systems (ARES) Lab. 61
62. Report Area
Design/Report Area
2
Ex: (0.18um Cell-Library: 1 gate ≈ 10 um2)
(0.13um Cell-Library: 1 gate ≈ 5 um2)
Ex:
(um2)
Advanced Reliable Systems (ARES) Lab. 62
63. Design View
List/Design View
All the block area are listed !!
Ex:
Ex:
Advanced Reliable Systems (ARES) Lab. 63
64. Report Timing
Timing/Report Timing
setup time
Critical Path
Ex:
max: setup time
min: hold time
Slack = Data Require Time – Data Arrival Time
Advanced Reliable Systems (ARES) Lab. 64
66. Timing Slack Histogram
Timing/Endpoint Slack Totally 190 paths are in the slack range between
0 to 1.78
Ex:
Resolution
Advanced Reliable Systems (ARES) Lab. 66
67. Edit Your Own Script File
For convenient, you should edit your own synthesis script file.
Whenever you want to synthesis a new design, you just only change
some parameters in this file.
Execute Script File
Setup/Execute Script
Ex:
Setup/Execute Script
Or use “source your_
script.dc” in dc shell
p _
command line
Advanced Reliable Systems (ARES) Lab. 67
68. Gate-Level Simulation
Include the Verilog model of standard cell and gate-level netlist to
your test bench Standard Cell Library
Add the following Synopsys directives to the test bench
Gate- Level Netlist
Add the following Synopsys directives to the test bench
*.sdf File Instance Name
Delay
Advanced Reliable Systems (ARES) Lab. 68