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ORGANIZED BY
JUNE 20TH
2019
Maud VINET
Quantum Hardware Program Manager
CEA Leti, France
From R&D to Market:
the industrialization challenge
FROM R&DTO MARKET
THE INDUSTRIALIZATION CHALLENGE
MaudVinet
Director of quantum hardware program
CEA-Leti
How to benefit from the quantum speed up?
Operation
frequency
Algo
optimization
Computer
architecture
1 million
1 second
1 day
RVanMeter, Communications of the ACM, 2013
DISAPPOINTED
LONELY
QUANTUM COMPUTING
Risks What if I fail?
What will my community
think of me?
My research is very
veryinteresting
Figures of merit vs applications
I need to understand
everything
From R&D to Market: the industrialization challenge
12 years ago, 2007
71nm
Samsung 7nm Fin pitch is 30nm
VLSI 2019, June 13th Kyoto
What he missed is sidewall image transfer
Risks ✓ Where is the end point?
✓ Who are the competitors?
✓ Who is on my team (why do
I need a team ☺)?
Semiconductor context
Year of 1st introduction2014 2016 2018 2020 2022
14nm 10nm 7nm 5nm 3nm
Artificial
intelligence
Matrix
formalism
HPC
Low Power
General
purpose
Computing
CMOS
Circuit Power management Standard cells height scaling
Architecture
Multicore 3D heterogeneous integration Photonic interconnects
In memory computing
25nm TBOX
20nm LG ISPD SiC
RSD
Si channel
Von Neumann
Heterogeneous computing
In memory computing Quantum computing
FDSOI
FROM R&DTO MARKET
SOMETHOUGHTS ONTHE
INDUSTRIALIZATION PATH
Challenges for hardware industrialization
Reliability
Technology
for scaling
Design
enablement
Ecosystem &
value chain
Reliability
Technology
for scaling
Design
enablement
Ecosystem &
value chain
Phase 1
Understand
variability
Control and
decrease variability
Yield
Phase 2 Phase 3
Device optimization and
fabrication influenced
benchmarking
Components developments
Components interfaces
Architecture definition
System integration
Packaging
Libraries
Physical Design Kit
Synthesis tools Full EDA ecosystem
Friendly used interfaces
Ecosystem creation
Value chain identification
Framework for
industrialization
Start-ups and licensing
Reliability
Technology
for scaling
Design
enablement
Ecosystem &
value chain
Phase 1
Understand
variability
Control and
decrease variability
Yield
Phase 2 Phase 3
Device optimization and
fabrication influenced
benchmarking
Components developments
Components interfaces
Architecture definition
System integration
Packaging
Libraries
Physical Design Kit
Synthesis tools Full EDA ecosystem
Friendly used interfaces
Ecosystem creation
Value chain identification
Framework for
industrialization
Start-ups and licensing
1st quantum revolution at work
• Industry
• Entrepreneurship
Engineering
➢ Large scale facilities
➢ Nanotechnologies
➢ Computer
sciences
➢ Mathematics
➢ Philosophy
➢ Social
sciences
students, researchers in fundamental quantum sciences
• Create the feeling of belonging to an adventure
• Leverage the physicits pessimism for risk analysis
and system design
Quantum physics
➢ Condensed matter
➢ Nanosciences
➢ Photonics
Collective intelligence, scout for the skills
Research organizations
Grenoble QuTech
Netherlands (Delft)
NQIT
UK (Oxford)
IQC
Canada (Waterloo)
NCCR-QSIT
Switzerland
(Zurich)
CQCCT
Australia
Creation
date
2019 2014 2014 2002 2011 2000
Structure
Leti + fundamental
research
TUDelft + TNO Hub national University Waterloo
IBM + universities
and EPFL
6 Universities
Funding Public PPP Public
PPP + private
patronage
PPP PPP
Size ~ 100 researchers ~145 researchers ~ 40 researchers ~30 researchers ~50 researchers ~100 researchers
QUANTECA
Grenoble
• Critical mass
• Skills diversity
• Leverage local specialties
QuantECA
Superconducting
circuits
Quantum optic
electronics
Spin qubits
Cryogenic electronics
Theory, modelization
and simulation
Fabrication technology
Large scale quantum integration
Q-Q
interfaces
Speed up in the number of quantum algorithms
Speed up in the quality of the qubits
Adapated from Schoelkopf et al
Speed up in the proposition of architectures
for large scale
M. Veldhorst et al. ,Nature
Comm. (2017)
M. Vinet et al., IEDM (2018)
R. Li et al., arXiv
1711.03807 (2017)
L.M.K. Vandersypen et al., npj
Quant. Inf. (2017)
J Gorman et al., npj Quant. Inf.
(2016)
QuCubeState of the art
?
Risk management
Indentifying synergies
Commonalities identification
Physics, Electronics,
Instrumentation
Algorithm
Alternative
paths
Si based QuCube technological
developments
Motivation and positioning
• The main objective is to demonstrate a quantum processor for simulation applications
• The novelty of is combine VLSI Si technology with quantum engineering and algorithms to find a full stack path
for quantum computing
• Quantum chips rely on Si spin qubits, quantum interface is based on cryoCMOS, compiler interacts at multilevel,
thus saving overheads
State of the art
Technological
modules
QuCube quantum
accelerator and up scaling
Materials
Integration for good qubits
2D tile
Control electronics
Optimized multi-scale
compiler
A programmable 100 qubit
quantum accelerator
Si based QuCube technological
developments
Motivation and positioning
• The main objective is to demonstrate a quantum processor for simulation applications
• The novelty of is combine VLSI Si technology with quantum engineering and algorithms to find a full stack path
for quantum computing
• Quantum chips rely on Si spin qubits, quantum interface is based on cryoCMOS, compiler interacts at multilevel,
thus saving overheads
State of the art
Technological
modules
QuCube quantum
accelerator and up scaling
Materials
Integration for good qubits
2D tile
Control electronics
Optimized multi-scale
compiler
A programmable 100 qubit
quantum accelerator
CMOS
technology
Memory
technology
5G
Communication
protocols
Patterning
Cryoelectronics example
COMET Programme l 28.03.2019
Short term Mid term Long term
Quantum computing
High performance computing
Spatial applications
| 25
1 qubit
2021
2024
Gen0
Application
processor
2030
Quantum simulation algorithm
Logical qubit demonstration
6 entangled
qubits
Tackle scientific questions
• 2 qubits gate
• Fidelity increase
• 2D tile for large scale
2018
Technological challenges
• Development of technological
modules for a million of qubits
• First 2D array of 100 to 256
interconnected qubits
Technology and biz
• Demonstration of all the
modules together
• Architecture yield
• Fabrication of a million of
qubits
• Value chain consolidation
• Cloud accesss
100 qubits
prototype
Error
correction
Start of industrialization?
QuCube silicon roadmap
GPU
CPU HPC
Parallel computing
CLOUD/HPC
Architecture
CPU
Processor
System
Tensor Flow
Processor (TPU)
Quantum computing
QPU
Applications
Programming
Languages
And APIs
Compilers
Quantum
error correction
Critical
components
Qubits
Arrays &
integration
system
architecture
SoftwarefocusHardwarefocus
Source BostonConsulting
Group
High performance computing users
Researchecosystem
Another brain
Mythic
Habana
Syntiant
COMET Programme l 28.03.2019

More Related Content

From R&D to Market: the industrialization challenge

  • 1. ORGANIZED BY JUNE 20TH 2019 Maud VINET Quantum Hardware Program Manager CEA Leti, France From R&D to Market: the industrialization challenge
  • 2. FROM R&DTO MARKET THE INDUSTRIALIZATION CHALLENGE MaudVinet Director of quantum hardware program CEA-Leti
  • 3. How to benefit from the quantum speed up? Operation frequency Algo optimization Computer architecture 1 million 1 second 1 day RVanMeter, Communications of the ACM, 2013 DISAPPOINTED LONELY
  • 5. Risks What if I fail? What will my community think of me? My research is very veryinteresting Figures of merit vs applications I need to understand everything
  • 7. 12 years ago, 2007 71nm Samsung 7nm Fin pitch is 30nm VLSI 2019, June 13th Kyoto What he missed is sidewall image transfer
  • 8. Risks ✓ Where is the end point? ✓ Who are the competitors? ✓ Who is on my team (why do I need a team ☺)?
  • 9. Semiconductor context Year of 1st introduction2014 2016 2018 2020 2022 14nm 10nm 7nm 5nm 3nm Artificial intelligence Matrix formalism HPC Low Power General purpose Computing CMOS Circuit Power management Standard cells height scaling Architecture Multicore 3D heterogeneous integration Photonic interconnects In memory computing 25nm TBOX 20nm LG ISPD SiC RSD Si channel Von Neumann Heterogeneous computing In memory computing Quantum computing FDSOI
  • 10. FROM R&DTO MARKET SOMETHOUGHTS ONTHE INDUSTRIALIZATION PATH
  • 11. Challenges for hardware industrialization Reliability Technology for scaling Design enablement Ecosystem & value chain
  • 12. Reliability Technology for scaling Design enablement Ecosystem & value chain Phase 1 Understand variability Control and decrease variability Yield Phase 2 Phase 3 Device optimization and fabrication influenced benchmarking Components developments Components interfaces Architecture definition System integration Packaging Libraries Physical Design Kit Synthesis tools Full EDA ecosystem Friendly used interfaces Ecosystem creation Value chain identification Framework for industrialization Start-ups and licensing
  • 13. Reliability Technology for scaling Design enablement Ecosystem & value chain Phase 1 Understand variability Control and decrease variability Yield Phase 2 Phase 3 Device optimization and fabrication influenced benchmarking Components developments Components interfaces Architecture definition System integration Packaging Libraries Physical Design Kit Synthesis tools Full EDA ecosystem Friendly used interfaces Ecosystem creation Value chain identification Framework for industrialization Start-ups and licensing
  • 14. 1st quantum revolution at work • Industry • Entrepreneurship Engineering ➢ Large scale facilities ➢ Nanotechnologies ➢ Computer sciences ➢ Mathematics ➢ Philosophy ➢ Social sciences students, researchers in fundamental quantum sciences • Create the feeling of belonging to an adventure • Leverage the physicits pessimism for risk analysis and system design Quantum physics ➢ Condensed matter ➢ Nanosciences ➢ Photonics Collective intelligence, scout for the skills
  • 15. Research organizations Grenoble QuTech Netherlands (Delft) NQIT UK (Oxford) IQC Canada (Waterloo) NCCR-QSIT Switzerland (Zurich) CQCCT Australia Creation date 2019 2014 2014 2002 2011 2000 Structure Leti + fundamental research TUDelft + TNO Hub national University Waterloo IBM + universities and EPFL 6 Universities Funding Public PPP Public PPP + private patronage PPP PPP Size ~ 100 researchers ~145 researchers ~ 40 researchers ~30 researchers ~50 researchers ~100 researchers QUANTECA Grenoble • Critical mass • Skills diversity • Leverage local specialties
  • 16. QuantECA Superconducting circuits Quantum optic electronics Spin qubits Cryogenic electronics Theory, modelization and simulation Fabrication technology Large scale quantum integration Q-Q interfaces
  • 17. Speed up in the number of quantum algorithms
  • 18. Speed up in the quality of the qubits Adapated from Schoelkopf et al
  • 19. Speed up in the proposition of architectures for large scale M. Veldhorst et al. ,Nature Comm. (2017) M. Vinet et al., IEDM (2018) R. Li et al., arXiv 1711.03807 (2017) L.M.K. Vandersypen et al., npj Quant. Inf. (2017) J Gorman et al., npj Quant. Inf. (2016)
  • 20. QuCubeState of the art ? Risk management
  • 21. Indentifying synergies Commonalities identification Physics, Electronics, Instrumentation Algorithm Alternative paths
  • 22. Si based QuCube technological developments Motivation and positioning • The main objective is to demonstrate a quantum processor for simulation applications • The novelty of is combine VLSI Si technology with quantum engineering and algorithms to find a full stack path for quantum computing • Quantum chips rely on Si spin qubits, quantum interface is based on cryoCMOS, compiler interacts at multilevel, thus saving overheads State of the art Technological modules QuCube quantum accelerator and up scaling Materials Integration for good qubits 2D tile Control electronics Optimized multi-scale compiler A programmable 100 qubit quantum accelerator
  • 23. Si based QuCube technological developments Motivation and positioning • The main objective is to demonstrate a quantum processor for simulation applications • The novelty of is combine VLSI Si technology with quantum engineering and algorithms to find a full stack path for quantum computing • Quantum chips rely on Si spin qubits, quantum interface is based on cryoCMOS, compiler interacts at multilevel, thus saving overheads State of the art Technological modules QuCube quantum accelerator and up scaling Materials Integration for good qubits 2D tile Control electronics Optimized multi-scale compiler A programmable 100 qubit quantum accelerator CMOS technology Memory technology 5G Communication protocols Patterning
  • 24. Cryoelectronics example COMET Programme l 28.03.2019 Short term Mid term Long term Quantum computing High performance computing Spatial applications
  • 25. | 25 1 qubit 2021 2024 Gen0 Application processor 2030 Quantum simulation algorithm Logical qubit demonstration 6 entangled qubits Tackle scientific questions • 2 qubits gate • Fidelity increase • 2D tile for large scale 2018 Technological challenges • Development of technological modules for a million of qubits • First 2D array of 100 to 256 interconnected qubits Technology and biz • Demonstration of all the modules together • Architecture yield • Fabrication of a million of qubits • Value chain consolidation • Cloud accesss 100 qubits prototype Error correction Start of industrialization? QuCube silicon roadmap
  • 26. GPU CPU HPC Parallel computing CLOUD/HPC Architecture CPU Processor System Tensor Flow Processor (TPU) Quantum computing QPU Applications Programming Languages And APIs Compilers Quantum error correction Critical components Qubits Arrays & integration system architecture SoftwarefocusHardwarefocus Source BostonConsulting Group High performance computing users Researchecosystem Another brain Mythic Habana Syntiant
  • 27. COMET Programme l 28.03.2019