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Memory and Processor Testing

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Sudhanshu Janwadkar
Sudhanshu Janwadkar

This document summarizes testing approaches for embedded processor cores and memory. It describes a Processor Self-Test (PST) architecture that uses a Linear Feedback Shift Register (LFSR) to generate random test patterns for the processor core and embedded memories. The PST program consists of instructions that exercise the processor core and memories. Built-in Self-Test (BIST) is also described as a method for testing embedded memories using on-chip circuits and minimizing external tester requirements, though it increases area and has speed limitations.

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Memory and Processor Testing By: Sudhanshu Janwadkar
Introduction • Embedded Processor Cores are used in many systems • Core based design offer advantages such as : reuse & Portability • Design that include processor cores present new challenges for testing as access to these embedded processor • Restrictions from access to pins of SoC
Processor Testing Architecture LFSR M F S R CORE Instruction Decode Logic TRAM SRAM Self Test • Processor Self Test Program Processor
Description TRAM consists of: • A Program and pattern for testing the Processor • A random Pattern Generator • Program and pattern for testing Embedded Memories • Program for testing other cores using UML(Unified Modeling Language) etc
Description(contd..) • The program consists of normal instructions that are executed by processor core. • The Data is provided by random pattern generated by LFSR • Faults are targeted during component test generation of the processor core. • Component test of the core can be provided as deterministic or random pattern
• Memory Architecture & Fault Models • DC / AC / Dynamic Tests • Built-in Self Testing Schemes • BIST architecture Memory Testing
Memory architecture
Fault models • Stuck-At Fault :- The logic value of a cell or a line is always 0 or 1. • Transition Fault :- A cell or a line that fails to undergo a 0 1 or a 1 0 Transition . • Coupling Fault :- A write operation to one cell changes the content of a second cell.
Neighborhood Pattern Sensitive Fault :- The content of a cell, or the ability to change its content, is influenced by the contents of some other cells in the memory. Address Decoder Fault (AF) :-  With a certain address, no cell will be accessed and a certain cell is never accessed.  With a certain address, multiple cells are accessed simultaneously.  A certain cell can be accessed by multiple addresses.
DC Parametric Testing • Open / Short test. • Power consumption test. • Leakage test. • Threshold test. • Output drive current test. • Output short current test.
AC Parametric Testing • Output signal: - the rise & fall times. • Relationship between input signals:– the setup & hold times. • Relationship between input and output signals:– the delay & access times. • Successive relationship between input and output signals:– the speed test.
Dynamic Faults • Recovery faults: − Sense amplifier recovery − Write recovery. • Retention faults: − Sleeping sickness − Refresh line stuck-at − Static data loss. • Bit-line precharge voltage imbalance faults.
BIST: Built In Self Testing  Advantages: – Minimal use of testers. – Can be used for embedded RAMs.  Disadvantages: – Silicon area overhead. – Speed; slow access time. – Extra pins or multiplexing pins. – Testability of the test hardware itself. – A high fault coverage is a challenge.
Typical Memory BISTArchitecture
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Memory and Processor Testing

  • 2. Introduction • Embedded Processor Cores are used in many systems • Core based design offer advantages such as : reuse & Portability • Design that include processor cores present new challenges for testing as access to these embedded processor • Restrictions from access to pins of SoC
  • 4. Description TRAM consists of: • A Program and pattern for testing the Processor • A random Pattern Generator • Program and pattern for testing Embedded Memories • Program for testing other cores using UML(Unified Modeling Language) etc
  • 5. Description(contd..) • The program consists of normal instructions that are executed by processor core. • The Data is provided by random pattern generated by LFSR • Faults are targeted during component test generation of the processor core. • Component test of the core can be provided as deterministic or random pattern
  • 6. • Memory Architecture & Fault Models • DC / AC / Dynamic Tests • Built-in Self Testing Schemes • BIST architecture Memory Testing
  • 8. Fault models • Stuck-At Fault :- The logic value of a cell or a line is always 0 or 1. • Transition Fault :- A cell or a line that fails to undergo a 0 1 or a 1 0 Transition . • Coupling Fault :- A write operation to one cell changes the content of a second cell.
  • 9. Neighborhood Pattern Sensitive Fault :- The content of a cell, or the ability to change its content, is influenced by the contents of some other cells in the memory. Address Decoder Fault (AF) :-  With a certain address, no cell will be accessed and a certain cell is never accessed.  With a certain address, multiple cells are accessed simultaneously.  A certain cell can be accessed by multiple addresses.
  • 10. DC Parametric Testing • Open / Short test. • Power consumption test. • Leakage test. • Threshold test. • Output drive current test. • Output short current test.
  • 11. AC Parametric Testing • Output signal: - the rise & fall times. • Relationship between input signals:– the setup & hold times. • Relationship between input and output signals:– the delay & access times. • Successive relationship between input and output signals:– the speed test.
  • 12. Dynamic Faults • Recovery faults: − Sense amplifier recovery − Write recovery. • Retention faults: − Sleeping sickness − Refresh line stuck-at − Static data loss. • Bit-line precharge voltage imbalance faults.
  • 13. BIST: Built In Self Testing  Advantages: – Minimal use of testers. – Can be used for embedded RAMs.  Disadvantages: – Silicon area overhead. – Speed; slow access time. – Extra pins or multiplexing pins. – Testability of the test hardware itself. – A high fault coverage is a challenge.