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Risc

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Piyush Rochwani
Piyush Rochwani

RISC and CISC are two different microprocessor architectures. RISC uses a reduced instruction set with simpler instructions that can operate at higher speeds, while CISC encodes more complex instructions directly. While CISC can complete fewer instructions per program by reducing the number needed, RISC shortens execution time by reducing the clock cycles per instruction through simpler interpretations. RISC also enables faster control units, pipelining for enhanced performance, and fewer transistors for lower manufacturing costs. Initially RISC gained popularity due to improvements in compiler and memory technologies. Today, most processors use a hybrid RISC/CISC approach to gain benefits of both architectures.

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RISC
RISC Reduced Instruction Set Computers  Microprocessor architecture  Designed to perform a set of smaller computer instructions so that it can operate at higher speeds
What RISC Does? Concept: Break Operation into Simple Sub- Operation. Eg:- Load X,Load Y,add X and Y,Store Z Problem: No Description of Instruction level Parallelism. Eg- how many CPU registers will it require? Examples:-ARM,PowerPC
CISC Complex Instruction Set Computers Concept: Encode the Instruction Directly Eg:-Add X & Y Put the Result in Z(For X,Y,Z Memory Addresses). Problem: Some Instructions Take more time than others. Eg:-x86,s390
The Comparison RISC systems shorten execution time by reducing the clock cycles per instruction (i.e. simple instructions take less time to interpret) CISC systems shorten execution time by reducing the number of instructions per program The simple instruction set of RISC machines takes less time to interpret plus less hardware Enables control unit to be hardwired for maximum speed Also allows room for performance enhancement such as pipelining Fewer instructions would mean fewer transistors, in turn less manufacturing cost The more complex and variable instruction set of CISC machines require more translation takes time as well more hardware . RISC architectures require a large number of CPU registers
Let’s Take a Walk in History! ->Compilers were hard to build especially for machines with registers ->Make machine do more work than software ->Have instructions load and store directly to memory (memory-to- memory operations) ->Software costs were rising and hardware costs were dropping ->Move as much functionality to hardware ->Magnetic core memory was used as main memory which was slow and expensive ->Minimize assembly code
->Compilers were improving ->Simple compilers found it difficult to use more complex instructions ->Optimizing compilers rarely needed more powerful instructions ->Caches allowed main memory to be accessed at similar speeds to control memory ->Semiconductor memory was replacing magnetic core memory ->Reduced performance gap between control and main memory Technology was Advancing
Hardware is ParallelWhile Software is Sequential More the Number of Transistors more work could be performed -- In Simple Words,our languague More the Memory,More Performance,More cores More powerful Processing. Eg:- A computer having 1 GB of RAM works more efficiently than a Computer with 256 MB RAM Software works Step by Step ,You do one thing than you do Another. Eg:- Booting up of PC,Installing Windows,any type of softwares etc.
Inception of RISC • 1974 – John Cocke (IBM) proved that 80% of work was done using only 20% of the instructions • Three RISC projects • IBM 801 machine (1974) • Berkeley’s RISC-I and RISC-II processors (1980) • Stanford’s MIPS processor (1981) • 1986 – announcement of first commercial RISC chip
RISC Approach • Use only simple instructions that can be executed within one clock cycle • Fewer transistors for instructions = more registers • Pipelining • Register-to-register operations • Operand reuse • Reduction of load/store
Pipelining IF – Instruction Fetch ID – Instruction Decode OF – Operand Fetch OE – Operand Execution OS – Operation Store IF ID O F OE O S IF ID O F OE O S IF ID O F OE O S IF ID O F OE O S IF ID O F OE O S IF ID O F OE O S Sequential Pipelined Clock Cycle ClockCycle Time
Risc
Risc
http://www.hardware secrets.com/article/In side-Pentium-4- Architecture/235/4
Use of RISC today • X86 is one of the only chips that retain CISC architecture • Large base of proprietary PC applications were written for X86 or compiled into X86 machine code • Intel was able to spend vast amounts of money on processor development to offset the RISC advantages enough to maintain PC market share • CISC and RISC architectures are nearly indistinguishable • CISC processors use pipelining and can complete multiple instructions per cycle • Transistor technology has allowed more room on chips allowing RISC to have more CISC like instruction
Other Advantages • New microprocessors can be developed and tested more quickly if being less complicated is one of it’s aims • Smaller instruction sets are easier for compiler programmers to use • Each type of processor has its benefits • Depends what type of device to be built • If it’s a small device ->RISC • If it’s a large device ->CISC
Thank YOU !

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Risc

  • 2. RISC Reduced Instruction Set Computers  Microprocessor architecture  Designed to perform a set of smaller computer instructions so that it can operate at higher speeds
  • 3. What RISC Does? Concept: Break Operation into Simple Sub- Operation. Eg:- Load X,Load Y,add X and Y,Store Z Problem: No Description of Instruction level Parallelism. Eg- how many CPU registers will it require? Examples:-ARM,PowerPC
  • 4. CISC Complex Instruction Set Computers Concept: Encode the Instruction Directly Eg:-Add X & Y Put the Result in Z(For X,Y,Z Memory Addresses). Problem: Some Instructions Take more time than others. Eg:-x86,s390
  • 5. The Comparison RISC systems shorten execution time by reducing the clock cycles per instruction (i.e. simple instructions take less time to interpret) CISC systems shorten execution time by reducing the number of instructions per program The simple instruction set of RISC machines takes less time to interpret plus less hardware Enables control unit to be hardwired for maximum speed Also allows room for performance enhancement such as pipelining Fewer instructions would mean fewer transistors, in turn less manufacturing cost The more complex and variable instruction set of CISC machines require more translation takes time as well more hardware . RISC architectures require a large number of CPU registers
  • 6. Let’s Take a Walk in History! ->Compilers were hard to build especially for machines with registers ->Make machine do more work than software ->Have instructions load and store directly to memory (memory-to- memory operations) ->Software costs were rising and hardware costs were dropping ->Move as much functionality to hardware ->Magnetic core memory was used as main memory which was slow and expensive ->Minimize assembly code
  • 7. ->Compilers were improving ->Simple compilers found it difficult to use more complex instructions ->Optimizing compilers rarely needed more powerful instructions ->Caches allowed main memory to be accessed at similar speeds to control memory ->Semiconductor memory was replacing magnetic core memory ->Reduced performance gap between control and main memory Technology was Advancing
  • 8. Hardware is ParallelWhile Software is Sequential More the Number of Transistors more work could be performed -- In Simple Words,our languague More the Memory,More Performance,More cores More powerful Processing. Eg:- A computer having 1 GB of RAM works more efficiently than a Computer with 256 MB RAM Software works Step by Step ,You do one thing than you do Another. Eg:- Booting up of PC,Installing Windows,any type of softwares etc.
  • 9. Inception of RISC • 1974 – John Cocke (IBM) proved that 80% of work was done using only 20% of the instructions • Three RISC projects • IBM 801 machine (1974) • Berkeley’s RISC-I and RISC-II processors (1980) • Stanford’s MIPS processor (1981) • 1986 – announcement of first commercial RISC chip
  • 10. RISC Approach • Use only simple instructions that can be executed within one clock cycle • Fewer transistors for instructions = more registers • Pipelining • Register-to-register operations • Operand reuse • Reduction of load/store
  • 11. Pipelining IF – Instruction Fetch ID – Instruction Decode OF – Operand Fetch OE – Operand Execution OS – Operation Store IF ID O F OE O S IF ID O F OE O S IF ID O F OE O S IF ID O F OE O S IF ID O F OE O S IF ID O F OE O S Sequential Pipelined Clock Cycle ClockCycle Time
  • 15. Use of RISC today • X86 is one of the only chips that retain CISC architecture • Large base of proprietary PC applications were written for X86 or compiled into X86 machine code • Intel was able to spend vast amounts of money on processor development to offset the RISC advantages enough to maintain PC market share • CISC and RISC architectures are nearly indistinguishable • CISC processors use pipelining and can complete multiple instructions per cycle • Transistor technology has allowed more room on chips allowing RISC to have more CISC like instruction
  • 16. Other Advantages • New microprocessors can be developed and tested more quickly if being less complicated is one of it’s aims • Smaller instruction sets are easier for compiler programmers to use • Each type of processor has its benefits • Depends what type of device to be built • If it’s a small device ->RISC • If it’s a large device ->CISC

Editor's Notes

  1. For my research topic I chose RISC which stands for reduced instruction set computers Its Design is What latest processors use,the reason I chose this topic.
  2. in 1974, John Cocke with IBM proved that about 80% of work was done using 20% of instructions This sparked three RISC based research projects IBM 801 machine in 1974 Berkeley’s RISC-I and RISC-II processors in 1980 And Stanford’s MIPS processor in 1981 Each of these projects took different paths in their research they all complemented and reinforced each others findings convincing many supporters In 1986 the computer industry began announcing commercial RISC chips