The document describes a workshop on Xilinx Vivado High Level Synthesis (HLS) tools held at NECST. The agenda includes an introduction to hardware design flow, the Vivado HLS design flow, kernel creation and optimization, and a hands-on example of implementing a vector addition using Vivado HLS. The example takes the participants through various implementation versions to optimize the kernel by applying directives for loop pipelining, array partitioning, and memory optimizations.
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More Related Content
SDAccel Design Contest: Vivado HLS
1. Courses @ NECST
Lorenzo Di Tucci <lorenzo.ditucci@polimi.it>
Emanuele Del Sozzo <emanuele.delsozzo@polimi.it>
Marco D. Santambrogio <marco.santambrogio@polimi.it>
Xilinx Vivado HLS
18/01/2018
2. Agenda
• Introduction to the Hardware Design Flow
• Vivado HLS:
–Design Flow
–Kernel Creation
–Communication Infrastructure
–Kernel Optimizations
• Hands-On Example
3. Installation Party
Use this Google Doc to provide your data
https://goo.gl/FRCG6y
First, install the VPN we have provided you.
(Mac: Tunnelblick - Windows/Linux: OpenVPN)
To SSH to the machine:
ssh <name>.<surname>@nags31.local.necst.it
password: user
4. Installation Party
You can change your password here:
http://changepassword.local.necst.it/
You can also RDP to the instance using
• Microsoft Remote Desktop (Microsoft/Mac OS)
• Remmina (Linux)
To connect to the machine, or change your password you must
have started the VPN.
5. Hardware Design Flow for HPC
• Hardware Design Flow (HDF): process to realize a
hardware module
• HDF for FPGAs can be seen as a 2 step process
8. The Hardware Design Flow
• CAD tools aims at alleviating the design on FPGA
• Designer still need to manually perform system
integration, driver generation and runtime management
9. The Hardware Design Flow
• CAD tools aims at alleviating the design on FPGA
• Designer still need to manually perform system
integration, driver generation and runtime management
10. The Hardware Design Flow
• CAD tools aims at alleviating the design on FPGA
• Designer still need to manually perform system
integration, driver generation and runtime management
11. Vivado HLS
• High Level Synthesis tools
• provided a high level description of a kernel, allows to
generate a HDL of the application
• increase the level of abstraction to ease the designing
process
• provides multiple hardware optimized libraries and
APIs
• directives driven architecture-aware synthesis
12. Vivado HLS Flow
Possibility to specify the kernel using High Level Code
- code must be refactored as a subset of C/C++ is supported
- no dynamic memory allocation
- Multiple API provided (arbitrary precision, mathematical functions, video library,
etc..)
- Possibility to specify a constraint file (clock uncertainty, clock period, target board)
C/C++
13. Vivado HLS Flow
Directives driven design and optimization
- necessary to specify interconnection with memory
(AXI4, AXI4Lite, AXI4-Stream)
- The designer still needs to have clear in mind what
architecture to implement
C/C++
IP Core Design
and
Optimization
14. Vivado HLS Flow
2 levels of emulation
- Software Emulation used to check functional
correctness of the application - does not guarantee
correctness on the FPGA
- Hardware Emulation check the correctness of the
logic generated by the synthesizer
C/C++
IP Core Design
and
Optimization
Software
Emulation
Hardware
Emulation
15. Vivado HLS Flow
C/C++
- Eventually, IP Core can be generated and exported so that it
can be used for the System Level Design Step.
- At each step of the pipeline, it is possible to come back to
the optimization phase
IP Core Design
and
Optimization
Software
Emulation
Hardware
Emulation
IP Core
Generation
16. Kernel Creation
• Not all the parts of an algorithm are suitable for
hardware acceleration
• First, it is necessary to profile the application to identify
the bottlenecks of the application, i.e. the most
compute intensive parts/kernels
• Then, it is possible to start adapting and optimizing the
kernels for the High Level Synthesis process
– define the communication infrastructure
– build the kernel architecture
17. Communication Infrastructure
• Mainly, 3 types of communication may be implemented
using AXI4 protocol:
– AXI-Lite (for control signals)
– Axi-Stream (to stream data)
– Axi-Master (direct connection with the memory)
• Vivado HLS provides directives to specify which type of
communication to implement
• However, the user has to develop the data transfer in
an efficient way
18. Kernel Optimizations
• Vivado HLS provides directives to optimize the kernel
• The directives may refer to:
– how to carry out the computation
• loop pipelining/unrolling
• function inlining
• dataflow
• resources to use for a certain computation
– how to store the data on FPGA memory
• array partitioning (block, cyclic, complete)
23. Example
• Now we are going to see how to implement a vector
addition of this form:
a = b + c*d
where a, b, c are vectors, and d is a constant
• We will go through all optimization steps with Vivado
HLS, from the project creation to the IP core generation
112. This is only the beginning!!
For more information, read Vivado HLS manual
https://www.xilinx.com/support/documentation/sw_ma
nuals/xilinx2017_2/ug902-vivado-high-level-synthesis.pdf
113. Feedbacks
• We are working at improving this course, would you
share your feedback for this lesson?
https://goo.gl/tLcWQj
114. Thank You for the
Attention!
Lorenzo Di Tucci
lorenzo.ditucci@polimi.it
Emanuele Del Sozzo
emanuele.delsozzo@polimi.it
Marco D. Santambrogio
marco.santambrogio@polimi.it