This document provides an overview of the Xilinx Vivado design suite for FPGA hardware design. It discusses the main steps in the hardware design flow including synthesis, place and route, and bitstream generation. It then demonstrates implementing designs for vector addition using both AXI master and AXI stream interfaces. The document walks through creating a Vivado project, adding IP cores like the MicroBlaze processor and memory interface, connecting the design, and generating a bitstream for the FPGA. It also discusses exporting the hardware to Xilinx SDK and running code on the MicroBlaze to test the designs.
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SDAccel Design Contest: Vivado
1. Courses @ NECST
Lorenzo Di Tucci <lorenzo.ditucci@polimi.it>
Emanuele Del Sozzo <emanuele.delsozzo@polimi.it>
Marco D. Santambrogio <marco.santambrogio@polimi.it>
Xilinx Vivado
25/01/2018
2. Agenda
• Hardware Design Flow (2nd step)
• Xilinx Vivado
–Synthesis
–Place & Route
–Bitstream Generation
• Hands on example: implementation of both master AXI
and AXI stream designs for vector addition using
Vivado and SDK
3. Reminder!
Use this Google Doc to provide your data
https://goo.gl/FRCG6y
First, install the VPN we have provided you.
(Mac: Tunnelblick - Windows/Linux: OpenVPN)
To SSH to the machine:
ssh <name>.<surname>@nags31.local.necst.it
password: user
4. Reminder!
You can change your password here:
http://changepassword.local.necst.it/
You can also RDP to the instance using
• Microsoft Remote Desktop (Microsoft/Mac OS)
• Remmina (Linux)
To connect to the machine, or change your password you must
have started the VPN.
5. Hardware Design Flow for HPC
• Hardware Design Flow (HDF): process to realize a
hardware module
• HDF for FPGAs can be seen as a 2 step process
7. The Hardware Design Flow
System integration, driver generation and runtime management
8. The Hardware Design Flow
System integration, driver generation and runtime management
9. The Hardware Design Flow
System integration, driver generation and runtime management
10. Vivado Design Suite
• Vivado Design Suite is a software suite for synthesis
and analysis of HDL designs
• Vivado enables developers to synthesize designs,
perform timing analysis, examine RTL diagrams,
simulate designs, and configure the target FPGA
• Starting from HDL, Vivado performs several steps to
eventually generate the bitstream
11. Vivado Main Steps
• Synthesis: translation from HDL to gate level
• Place: placing of all the logic components on the FPGA
• Route: design of all the wires needed to connect the
placed components
• Bitstream: generation of FPGA configuration file
42. MIG Customization
• text
This page allows to add / customize clock signals
MIG will generate two clocks:
- ui_clk (200Mhz)
- ui_addn_clk_0 (100Mhz)
120. AXI Stream Design
• Let’s know implement the design for the streaming
version of the vector addition
• For this design, we will use the DMA IP
• All the steps until the “MIG + Microblaze Design” slide
do not change
154. Next steps
It is now possible to repeat the steps done for the previous
design:
–enable JTAG UART on the MDM block
–add AXI Timer IP
–Run Validation
–Create HDL Wrapper
–Run Generate Bitstream
–Export Hardware
–Run SDK
157. SDK steps
After exporting the hardware from Vivado:
– Launch SDK
– Create the project
– Test the “helloworld”
– Use the provided code to evaluate the design
158. Summary
• Vivado toolchain allows developers to design both the
IP they want to accelerate and the overall system
• Vivado/Vivado HLS examples, and SDK code are
available on nags31 server in /sdaccel_contest folder
• Next lectures will focus on SDAccel toolchain
159. Feedbacks
• We are working at improving this course, would you
share your feedback for this lesson?
https://goo.gl/tLcWQj
160. Thank You for the
Attention!
Lorenzo Di Tucci
lorenzo.ditucci@polimi.it
Emanuele Del Sozzo
emanuele.delsozzo@polimi.it
Marco D. Santambrogio
marco.santambrogio@polimi.it