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International journal of VLSI design & Communication Systems (VLSICS) is a bi monthly open access peer-reviewed journal that publishes articles which contribute new results in all areas of VLSI Design & Communications. The goal of this journal is to bring together researchers and practitioners from academia and industry to focus on advanced VLSI Design & communication concepts and establishing new collaborations in these areas.
Tags
vlsi circuits
vlsi design
reliability
computer-aided design (cad)
post-cmos vlsi
wireless communications
emerging technologies
testing
design
vlsi applications
fault-tolerance
molecular
low power and power aware design
security
low power
sensor networks
video
nano electronics
biological and quantum computing
communication systems
intellectual property creating and sharing
vlsi
fpga
cmos
vlsi applications (communications
communications
leakage power
phd
wireless
wireless networks
full adder
sram
soc
phdstudent
etc)
reversible logic
design vlsi circuits computer-aided design (cad) l
dsp
finfet
biological and quantum computing intellectual prop
fault-tolerance emerging technologies post-cmos vl
etc) nano electronics
high speed
pattern recognition
pipeline
xilinx
write delay
image processing
digital image processing
analog testing
visualization
communication
digital signal processing (dsp)
transistor stacking
universal verification methodology (uvm)
etc) * nano electronics
biological and quantum computing * intellectua
matlab
leakage current
fault-tolerance * emerging technologies *
analog-to-digital converter
design * vlsi circuits * computer-aided design
vlsi circuit
noise figure
delay
power gating
dibl
power dissipation
static random access memory
image formation
fir
iir
sleep transistor
low-power
simulation
static noise margin
read delay
garbage output
45nm technology
lna
verilog
dram
domino logic
power consumption
power management
voltage control circuit
regularity
nanotechnology
standby power
reverse body bias
dual threshold design
low power.
adc
mosfet
floating gate mosfet
snm
network on chip
dynamic power
adiabatic logic
low voltage
low power design
nanoelectronics
pass transistor logic
quantum computing
cryptography
assist circuitry
single-port
fault simulation
adaptive biasing
transistor modeling.
power delivery
amba(advance microcontroller bus architecture)
dcc
sensors
roba architecture
integrator
control voltage generator
frequency range
high speed multiplier
quantum dot
ahb2apb
error analysis
efficient
stepwise charging
reversible gate
approximate computing
spartan3e
simulink
mips risc processor
register exchange method
adiabatic
ecu
scheduling
oem
accuracy
ber
vlsi technology
dsp processing
motion estimation
axi(advanced extensible interface)
hevc
phase locked loop (pll)
network-on-chip
hardware security
uvm(universal verification methodology)
side-channel analysis
quaternary logic
functional coverage
fault injection
synthesizable active agent
universal serial bus (usb)
scan-based attack
testability
link training and status state machine (ltssm)
kogge stone adder
embedded rams
security.
sub threshold leakage
adiabatic logic.
energy harvesting
impalntablr bio-medical devices
pacemaker
voltage scaling
gate diffusion input (gdi)
carry save adder (csa)
traceback method
back gate biasing.
carbon nano-apex
error rate
power dissipation.
concurrent processing
field emission
lattice network
vlsi researcher
crosstalk
carbon nano-apex emission
concurrent computing
formal symmetrization
lattice networks
research
quantum cost
mri
alu
flip-flop
eeg
voltage stacking
power gain
rf cmos
asynchronous
carbon nanotube field effect transistor
mtncl
dynamic gesture recognition
implicit interaction
embedded systems
edge point sequential extraction
least-squares method
segmentation
hspice
current mirror
context information
slew rate
standby start-up circuit
transconductance
operational amplifier
very large scale integration (vlsi).
multimedia
slack based genetic algorithm
functional verification
cntfet
questasim
approximate computing (ac)
complementary metal oxide semiconductor
sub-threshold circuits
reusable vip
spi master core
amplifier
gds format.
cdma
ddc file
zigzag
fifo
system-on-chip
on-chip routing switch
hol blocking
virtual output queuing
scheduler
2d mesh
cmfb
short channel effects (sces)
hybrid register exchange method
planar mosfet
grooved mosfet
concave corner
corner angle
deep submicron regime
bus encoding
vhdl
transmission gate logic
poly-thiophene pt
ripple carry adder
thin film transistor tft.
jpeg
quantization
digital down-counter
channel.
power line carrier communication
edge detection
xilinx system generator
state dependent
spare cell
eco cell
etc
logic circuits
molecular electronics
resonant tunneling diode (rtd)
feynman gates
fredkin gate
nmos & pass transistor.
deblocking filter
nios-ii soft processor
engineering change order (eco)
garbage
rtl.
exclusive-or (xor)
exclusive-nor (xnor)
automatic test pattern generation (atpg)
fault coverage
work function
32nm technology
sram cell
islip
fft
dwt
ofdm
through silicon via.
lifting scheme
vlsi architecture
three dimensional integration
peak temperature
hotspot
snm and process variations.
amba
12-t sram cell
body effect
bota
ota
bulk-driven mos
tsmc
multi-vdd
application specific integrated circuit
digital up-counter
stuck-at fault
constant input
full subtractor
stability
multism
bipolar junction transistor
fabrication
4tdram
3tdram
3t1d dram
library free synthesis
on the fly mapping
critical path
cell re-ordering
recycling folded cascode
lock range
oscillator
injection-locked
clock and data recovery
eye diagram
high vth
high performance vlsi circuits
voltage control
multicore
digital-to-analog converter
enob
encoder
dtmos
low power circuit
asynchronous design
power
hardware description language (hdl)
discrete wavelet transform (dwt)
fault.
rfid
return losses
nsga-ii algorithm
cnt
high performance & power delay product
n-bit reversible comparator
virtual allocator
phase frequency detector
gate diffusion cell
voltage controlled oscillator
charge pump.
trans - conductance.
polarization
algan/gan modfets
drain - conductance
cut-off frequency
regulated cascode
low-voltage & low-power
molecular communication
nano networks
diffusion channel
channel capacity
rf
dc
optical illumination
ac
inventive gate
low vth
dynamic threshold
active mode leakage reduction
minimum leakage vector (mlv)
standby mode
band to band tunneling (btbt)
dynamic range
single precision
instruction set
analog multiplexer
pass transistors
current mode logic
microcontroller
gdi
pae
speed
subthreshold
virtual channel
coulomb oscillation
coulomb blockade
single-electron transistor
primitive
characteristic polynomial
bist
misr
lfsr
field programmability
floating gate fet
square wave generator
reversible parallel binary adder/subtractor.
garbage input/output
test minimization.
heuristic approach
fault library
adaptive scheduled fault detection
mos resistor
linear range
wilson mirror
1.5 bit stage
hybrid system
fast fourier transform (fft)
fault dictionary
fault diagnosis
encoding
cmos inverter
cad
low power consumption
itrs
high performance (hp)
overlap
underlap
triple gate
double gate
search based memory
key pipelining
aes pipelining
static and dynamic
current substractor.
opamp
mix-column
sub-channel
advanced encryption standard
sub-threshold
bio-medical
kogge-stone adder
offset quadrature phase shift keying modulator and
symbol-to-chip
bit-to-symbol
cyclic redundancy check
min
quaternary voltage mode
multiple-valued logic (mvl)
noise shaping
autosar
snr
temperature-insensitive
elastic buffer
mac
bulk-input
neighbor aps
trajectory of mn
gps (global positioning system)
ieee 802.11
photovoltage
photodetectors
schottky junction
optoelectronics
lut & sdr
gsm
bram
asic
voltage-controlled oscillator (vco)
modulo-n addition and multiplication
multiple-valued logic
quality of service.
wide band code division multiple access
call admission control
uvm
analog and mixed-signal
circuit metrics
precompilation
image coding and compression
audio/speech processing and coding
watermarking
télécommunications
mimo
symmetric function
image segmentation
* vlsi applications
signal identification
technology
back gate biasing
computer vision
signal
brent kung adder
hdl
signal routing
parallel prefix adders
cmos vlsi
design for test
power delay product (pdp)
face recognition
sum of absolute difference
data compression
random access scan
average power
elaboration
analog and mixed signal processing
compilation
emd
fault model
test generation
module interconnections
design error
imf
state retention
mimo.
concurrency
argument
• visualization
journalism
machine learning
artificial intelligence
sv
synthesis
mean error distance
multiplier
noc
error metrics
layout congestion
vlsi communication
lifting scheme (ls)
digital clock manager
filter bank (fb).
modulo rns division
residue number system (rns)
integer wavelet transform (iwt)
average latency
deflection routing
minimal buffering
advanced verification methodology
test bench.
verification simulation software
firefly algorithm
transistor sizing
iterative symmetry decomposition
low power vlsi circuit.
binary compressor
alu designing
sctmr
scan chains & sctmr.
critical applications
fault recovery
tolerance
firm ip core
i2c protocols
asic designing
serial bus interfaces
ip designing.
on-chip communications
nano-apex emission.
field programming gate array (fpga)
application specific integrated circuit (asic)
reconfigurable dsp processor
software defined radio (sdr)
union of graph
signal flow graph (sfg)
digital signal processing (dsp) processor
row driver
column driver
liquid crystal display (lcd)
gamma correction
differential mux
average power consumption
ft
process variations
statistical modelling
design of experiments
analog signals.
sub threshold
multiplexer
source coupled logic
multimedia systems and devices
co-ordinate evaluation
galois addition and multiplication.
coding and transmission
image and video processing & analysis
computer graphics and visualization
sub- threshold
dynamic threshold mos inverter
propagation delay
reversible decoder etc.
noise-margin
low power circuit; carbon nanotube filed effect tr
variable threshold mos inverter
femtocells; handover; soft handover; hard handover
minimum transition register exchange method.
dac
combinationalcircuits
stuck_open
stuck_short
fpga (field programmable gate array).
atm (automated teller machine)
hdl (hardware description language)
subthreshold slope (ss)
impact ionization
barrier tunneling
schottky-contacts
analog- to- digital converter
successive approximation
split array
digital- to- analog converter
charge redistribution
benchmark circuit& noise
iscas85
logic gate
soft error
android
api
ndef
nfc
class ab output stage
• video signal processing
• data mining techniques
mixed signal processing
genetic algorithm
mmic
doherty power amplifier
phase shifter
snr and low power.
biomedica
remote sensing
• motion detection
• communication
networks
• object detection
quasi-cyclic -low-density-parity-check (qc-ldpc)
richardson and urbanke lower- triangular algorithm
wlan (ieee802.11n)
shape representation
low pass filter.
switched-capacitor
finite impulse response (fir)
parallel fir
carry-look-ahead adder (cla)
booth multiplier
forward body bias
multi threshold.
multi vth
swing limited interconnect circuit
boostable repeater
buffer insertion
adaptive filters
• image acquisition & medical image processing
delay stages
time to digital converter (tdc)
gated ring oscillator (gro)
pvt corners.
analog data selector
• image acquisition & medical image processing • p
• depend3d and stereo imaging
digital clock manager.
reversible decoder
power supply.
nano transistors
carbon nanotube filed effect transistors
• image segmentation
• face recognition
power supply. 1. introduction
surface reconstruction
autosar.
• multi-view geometry
• dsp implementation
• distributed source coding
transient noise assessment
aural noise
spectral exploration
digital multiplier
power and delay
modified booth multiplier (mbe)
high performance architecture
unate function
max
boolean decomposition
rca
verilog hdl.
cia
cla
rf cmoslna
wimax
symmetric function.
brent kung adder.
finite impulse response (fir) filter
clock power
regularity.
datapath
hdmi
serial interface
usb
supply current
vlsi design & communication systems
verilog a
nano-technology.
radix-2 fft
radix-4 fft
single path delay commutator
pn (phase noise analy
vco (voltage controlled oscillator)
lpf (low pass filter)
pd (phase detector)
pll (phase locked loop)
read/write assist circuitry
standby start-up
quaternary current mode
thermal hot spots
kink energy
level triggered flip-flop
quantum-dot cellular automata (qca)
counter
nanometre scale.
iterative dfg
non-canonical.
cutset retiming
folding
vlsi signal processing
signal assessment
gbps
* wireless communications
tri-state inverters
boolean algebra
clustering. 1. introduction
karnaugh map
digital logic circuit
cascode topology 1. introduction
rfic
impedance matching
power optimization
recursive encoder/decoder
bulk driven.
static d flip-flop
dual-edge triggered
vedic multiplier.
anurupye
nikhilam navatashcaramam dashatah
urdhva tiryagbhyam
shannon’s expansion theorem
carry propagate adder
low power vlsi design.
gate diffusion input technique
flash analog to digital converter
resistorless
switched inverter scheme (sis)
cmos 45nm
read/write transitions
dual sub-threshold
dpa resistance
side channel attack
acceptance probabi
risa
clock- gati ng.
* low power
interrupt
risc
reversible comparator
signed ar ithmetic
cade nce
fpgas
validation
testbench
asics
a
v
singal processing
mobile
post-cmosvlsi
power clock
diode
adiabatic logic circuits
energy
* design
* post-cmosvlsi
scale free cordic
systolic array
pipeline architecture.
integrated circuit
spatial wave-function switched fet
digitalto- analog converter (dac)
analog-to-digital converter (adc)
web design
graphic design
power delay product (pdp).
wireless sensor network
education
embedded architecture
middleware
real time system
mobile networks
call for papers
vlsics
journals
articles
university
privacy
power evaluation
mips architecture
clock gating
simulation.
performance optimization
area & power
performance analysis
zbt sram
low drop-out
low quiescent current
voltage regulator
lector technique.
cmos buffer
quiescent current
class-ab
rail-to-rail
finite state machine; parking system; virtex- 5
arithmetic circuit
logic circuit
parity preserving gates
fault tolerant full adder
von neumann landauer limit
reversible computing
cell library
noise margin
bidirectional buffer
shielding
electronics
skewing
rotation mode
roc
vectoring mode
acceptance probability
karatsuba ofman multiplier
gaussian image filter
mitchell log multiplier
phase lock loop (pll)
delay lock loop (dll)
current balanced logic (cbl)
current starved inverter (csi)
source coupled logic (scl)
comparator
flash adc.
variable switching voltage
threshold inverter quantization
drains circuit
cascaded stages and source driver
intellectual property creating
buffer circuits
discrete cosine transform (dct
jldmsg (junctionless dual material surrounding gat
short channel effects (sce).
mrfb
filter bank
da based multiplication
multipliers
transistor stacking.
array signal processing
implementation
12 lead ecg
image acquisition & medical image processing
pattern recognition and analysis
face recognition & super-resolution imaging
3d and surface reconstruction
digital & mobile signal processing
data mining techniques
detection and estimation of signal parameters
bme gate
pass transistor logic.
leakage power and switching probability.
signal processing
signal and image processing
nonlinear signals and systems
opencircuit fault.
formal methods in conformance
redundancy bit removal
algorithm
hybrid register exchange metho
memoryless hrem
positive feed back
organic thin film transistors
radio frequency identification
dg-pnin tfet
tunnel field effect transistor (tfet)
ion/ioff ratio
dg-pin tfet
psnr
reverse converters
chinese remainder theorem
residue arithmetic
and embedded block ram
ieee754 standard floating point format
look-up tables
complex floating point arithmetic hardware
on-chip ram
processor hardware
and embedded block ram
information
ieee754 standard floating point format
look-up tables
complex floating point arithmetic hardware
data mining
on-chip ram
processor hardware
matching networks
s-parameters
output power
database
body-bia s.
data stucture
transmission gate
gate diffusion input
acceptance probabilit
digital circuits
internet of things technology
storage and retrieval
memory built in self-test (mbi
built in self-repair (bisr)
test methodology
ate
automated test equipment
dcl
pin parametric unit
variable-amplitude dithering
iterative symmetry decompositi
digital calibration
mtcmos inverter
high power
pocket dgtfet
* wireless communications
xrtl tasks/functions (xtf)
emulator
transactor interface (tif)
universal verification component (uvc)
verification ip (vip).
testbench-xpress (tbx)
* post-cmos vlsi
systemverilog
acceleratable uvc
standard co-emulation api: modelling interface (sc
field programmable gate arrays
adders
keywords sram
pass logic implementations
logic devices
low- power
power delay product
layout design.
deadlock recovery
deadlock detection
routing algorithm
bus enhanced noc.
aes
mixcolumn
vhdl code
encryption
razor
leakage power and switching probability
cmos transmission logic
meta-stability detector
dvs
lifting based scheme
field-programmable gate-array (fpga)
pipeline architecture
reduced bit precision
fixed point
scs
mc-cdma
uwb
carbon nanotube field-effect transistor (cntfet)
key generation
elliptic curve cryptography
mud
cmos ring oscillator (ro)
bit/block errors.
memory section addressing
progressive coding
memory fault
transmission gates
stacking effect
process technology
parasitic fringe capacitance.
hetero-gate
band-to-band tunnelling
integrated circuit (ic)
phase noise
center frequency of oscillation
walsh code
router
proposed parity preserving gate
constant inputs and proposed fault tolerant full a
carry skip adder
carry look ahead adder
average power dissipation
radix -2 modified booth algorithm
digital signal processing
spurious power suppression technique
bme gate.
channel
mba
snm and process variations
linearity
gate stack
dg-tfet
analog
signal skew
effective thermal conductivity
fine mesh(fm)
coarse mesh(cm)
heat sink
source point
target point
medical imaging
integrated circuits
continuous domain
floorplaning
hotspots
3d chips
technology independent mapping
adder topologies
multiplexer based adders
logical effort
delay calculation
10 transistor serf adder
svl circuit
stand-by leakage power
aca
apa
discrete time sigma delta modulation
oversampling
cic decimation filter
switching activity
equal / unequal rise time
simultaneous switching
power saving
capacitance[5]
mealy and moore machines
fsm decomposition [2]
nanowire mosfet.
interface traps
hot carrier effect
fixed charges
channel length modulation
atlas-3d
crossbar
routing
virtex – 6 low power.
virtex-5
virtex-4
verilog hdl
truncated multiplier
spartan-3e
fast addition
field programmable gate array (fpga)
double edge triggered(det ) d flipflop(dff )
ring-counter
gated-clock
first-in–first-out (fifo)
gc-element
analog to digital converter.
fat tree tc-bc encoder
tiq
wishbone interface
wishbone bus
soc buses
phase detector
loop filter
adpll
dco
reversibility
miniaturization
analog multipliers
analog integrated circuits
carbon nanotube fet
data weighted averaging
dynamic element matching
bandpass σ∆ modulator
sigma delta modulation
over sampling
tmr
virtuoso
cadence
medical image
gabor algorithm
vlsi circuits computer-aided design (cad) low powe
sub-threshold region
ultra low power
threshold voltage (vt)
cordic algorithm
independent-gate (ig)
gate workfunction
dual-metal gate (dmg)
rf switch
wireless network
radio-frequency
low noise amplifier
advanced design system
image compression.
vlsi architectures
lifting schemes
discrete wavelet transform
hybrid full adder
xor-xnor circuit
very large scale integrated (vlsi)circuits
back gatebiasing.
neural network architecture
back propagation algorithm
corrector.
detector
decoder
write-ability
full-adder cell
basic gates.
biological
ptl
pdp
full adder & vlsi.
stacking technique
self cascode
folded cascode ota
meter count
efficiency
loom machine
carbon nano-tube
carbon nano-tube field effect transistor
low power full adder
moore’s law.
gain
trans-conductance
analog and mixed signal (ams)
silvaco tcad tool
dmg mosfet
gate leakage
sram and vlsi.
cmos logic
hysteresis.
current comparator
current mode
static ram (sram)
read stability
n-curve
interconnects
ultra-low voltage
coupling
fpga spartan 3 development board
vending machine
asynchronous logic
fsm
biological and wireless communications
delay-insensitive
schmitt-triggered
silicon-on-insulator
bus-invert
inductance effects
rsa.
modular multiplication
sign estimation technique
sign detection
carry-save adder
efficient architecture
carry select adder.
carry increment adder
carry save adder
cnfet
input third order intercept point (iip3)
shunt-series peaking
dual source degenerated current reuse
sub-micron regimes.
scanflop
analog to digital converter (adc)
opamp sharing
memory effect
system verilog
register interface(s)
video data interface(s)
universal verification component(uvc)
carbon nanotube
mulitple valued logic
vlsi.
register and memory model
ip-xact
incisive software extension (isx)
virtual register interface (vri)
verification abstraction layer(val)
uvm-ml.
reversible logic gates
toffoli gates
partial products
future computing.
navigation
rtl schematic
low power multipliers
column bypass multiplier
2-d bypass multiplier
reduced switching activity
fast fourier transform
high performance voltage-controlled oscillator (vc
phase-locked loop (pll)
eda tool.
diametrical 2d mesh routing
on-chip communication
vco
baseband pll
charge pump pll
pll
redundancy
hardware controller
fault tolerance
high frequency
current buffer compensation
cmos analog circuit
mobility & mole fraction.
drain current
channel thickness
biaxial strained
flash analog to digital converter
sampling switch
peak power
extended xy
track and hold circuit
scan chain.
latch
test time
double edge triggered flipflop
zero padding.
gals
ternary tree network
data synchronization
reconfigurable computing
domain-specific architecture
reconfigurable architecture
coarse-grained fabric
test vector
galois addition and multiplication
compaction
iscas
atpg
pareto-optimal
fine-grained dvs
branch-and- bound
low power vlsi
bus transition reduction
arithmetic coding
compressed code systems.
computer-aided design (cad
exclusive -or
equivalence
implication
inhibition
inverse.
nano scale electronic design and applications
face and gesture
filter design and structures
fsm optimization
synthesis constraints
state encoding
logic optimization
minority function
cntfet technology
logic gates
pbch
pmch
pdcch
pdsch
pcfich
mbsfn
combinational circuits
mbms
memory testing
error correction codes
matrix codes
multiple error detection
co-ordinate evaluation.
multiple error correction.
dual-threshold
subthreshold leakage
gate oxide tunneling
leakage current.
crypto processor
prime field
binary field.
gilbert cell
noise spectral density
total harmonic distortion
design vlsi circuits computer-aided design (cad)
fault-tolerance emerging technologies post-cmos
discrete cosine transform (dct)
etc) nano electronics
biological and quantum computing intellectual pro
gate all around(gaa)
radio frequency identification rfid
organic thin film transistors otft
serf adder
tg finfet
positive feed back adiabatic logic
high k gate oxide
silicon-on-insulator(soi)
short channel effect
subthreshold slope
3-d sentaurus tcad tool.
two phase clocked
energy recovery
split-level
diode based logic
lphs (low power high speed).
rtd
spice
threshold
memoryless hrem.
multi-channel
swsfets
march c-
modified march c- algorithm
concurrent technique
complexity
traditional march tests.
buffer
dynamic circuit
precharge pulse
barrier lowering
corba
cylindrical surround gate (csg) mosfet
merit factor
polyphase sequence
quaternary sequence
ternary sequence
pulse compression
psrr
temperature coefficient
bgr
fringing field
process and device simulation
sces
soi finfets
sub threshold slope
synthesis.
tcad
tlg
pseudo nmos
dual rail domino logic
static cmos logic
comparator.
interval arithmetic
floating-point
wireless application.
rf design
low noise amplifier (lna)
90nm technology
bics
iddq testing
resistive path
short (bridging) defect
operational amplifier (op amp)
noc routing
nano-cmos technology
areaoptimization.
power ooptimization
turbo decoder
turbo encoder
single/multiple input signature register
linear feedback shift register
tool
computer-aided design
test
bist generator
multiple outputs
track
channel routing
redundancy bit removal algorithm
manhattan routing model
vcg & merging.
delayed flip-flop (d-ff)
analog and mixed-signal circuit
formal methods in conformance testing
phase frequency detector (pfd)
opencircuit fault
true signal phase clock (tspc)
divider (div)
voltage controlled oscillator (vco)
forbidden pattern free
micron
coupling capacitance
parasitic
charge pump (cp)
flash adc
xor gate based encoder
low pass filter (lpf)
bridge full adder.
hybrid xor-xnor circuit
very large scale integrated (vlsi) circuits
power-delay product (pdp)
moscap
dynamic circuits
majority-not gate
leakage current .
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