Article

A Complete Network-On-Chip Emulation Framework

Authors:

F. CatthoorAuthors Info & Claims

DATE '05: Proceedings of the conference on Design, Automation and Test in Europe - Volume 1

Pages 246 - 251

https://doi.org/10.1109/DATE.2005.5

Published: 07 March 2005 Publication History

Abstract

Current Systems-On-Chip (SoC) execute applications that demand extensive parallel processing. Networks-On-Chip (NoC) provide a structured way of realizing interconnections on silicon, and obviate the limitations of bus-based solution. NoCs can have regular or ad hoc topologies, and functional validation is essential to assess their correctness and performance. In this paper, we present a flexible emulation environment implemented on an FPGA that is suitable to explore, evaluate and compare a wide range of NoC solutions with a very limited effort. Our experimental results show a speed-up of four orders of magnitude with respect to cycle-accurate HDL simulation, while retaining cycle accuracy. With our emulation framework, designers can explore and optimize a various range of solutions, as well as characterize quickly performance figures.

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Cited By

Arndt OSpindeldreier CWohnrade KPfefferkorn DNeuenhahn MBlume H(2017)FPGA Accelerated NoC-SimulationProceedings of the 8th International Symposium on Highly Efficient Accelerators and Reconfigurable Technologies10.1145/3120895.3120916(1-6)Online publication date: 7-Jun-2017
https://dl.acm.org/doi/10.1145/3120895.3120916
Aghaei BKhademzadeh AReshadi MBadie K(2017)Link TestingJournal of Electronic Testing: Theory and Applications10.1007/s10836-017-5646-033:2(209-225)Online publication date: 1-Apr-2017
https://dl.acm.org/doi/10.1007/s10836-017-5646-0
Qian ZBogdan PTsui CMarculescu R(2016)Performance Evaluation of NoC-Based Multicore SystemsACM Transactions on Design Automation of Electronic Systems10.1145/287063321:3(1-38)Online publication date: 11-May-2016
https://dl.acm.org/doi/10.1145/2870633
Show More Cited By

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A Complete Network-On-Chip Emulation Framework

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cover image ACM Conferences

DATE '05: Proceedings of the conference on Design, Automation and Test in Europe - Volume 1

March 2005

630 pages

ISBN:0769522882

Sponsors

SIGDA: ACM Special Interest Group on Design Automation

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IEEE Computer Society

United States

Publication History

Published: 07 March 2005

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DATE05: Design, Automation and Test in Europe

March 7 - 11, 2005

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Overall Acceptance Rate 518 of 1,794 submissions, 29%

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Cited By

Arndt OSpindeldreier CWohnrade KPfefferkorn DNeuenhahn MBlume H(2017)FPGA Accelerated NoC-SimulationProceedings of the 8th International Symposium on Highly Efficient Accelerators and Reconfigurable Technologies10.1145/3120895.3120916(1-6)Online publication date: 7-Jun-2017
https://dl.acm.org/doi/10.1145/3120895.3120916
Aghaei BKhademzadeh AReshadi MBadie K(2017)Link TestingJournal of Electronic Testing: Theory and Applications10.1007/s10836-017-5646-033:2(209-225)Online publication date: 1-Apr-2017
https://dl.acm.org/doi/10.1007/s10836-017-5646-0
Qian ZBogdan PTsui CMarculescu R(2016)Performance Evaluation of NoC-Based Multicore SystemsACM Transactions on Design Automation of Electronic Systems10.1145/287063321:3(1-38)Online publication date: 11-May-2016
https://dl.acm.org/doi/10.1145/2870633
Romanov AIvannikov A(2016)SystemC NoC simulation as the alternative to the HDL and high-level modelingProceedings of the 18th Conference of Open Innovations Association FRUCT10.1109/FRUCT-ISPIT.2016.7561540(285-290)Online publication date: 25-Apr-2016
https://dl.acm.org/doi/10.1109/FRUCT-ISPIT.2016.7561540
Naruko THiraki KEbrahimi MGoehringer D(2015)FOLCSProceedings of the 3rd International Workshop on Many-core Embedded Systems10.1145/2768177.2768182(25-32)Online publication date: 13-Jun-2015
https://dl.acm.org/doi/10.1145/2768177.2768182
Chaker HCudennec LDahmani SGogniat GSepúlveda MWang ZPetoumenos PLeather H(2015)Cycle-based Model to Evaluate Consistency Protocols within a Multi-protocol Compilation Tool-chainProceedings of the 2015 International Workshop on Code Optimisation for Multi and Many Cores10.1145/2723772.2723779(1-10)Online publication date: 8-Feb-2015
https://dl.acm.org/doi/10.1145/2723772.2723779
Abba SLee J(2014)A parametric-based performance evaluation and design trade-offs for interconnect architectures using FPGAs for networks-on-chipMicroprocessors & Microsystems10.1016/j.micpro.2014.04.01138:5(375-398)Online publication date: 1-Jul-2014
https://dl.acm.org/doi/10.1016/j.micpro.2014.04.011
Kinsy MPellauer MDevadas SHutchings BBetz V(2013)HeraclesProceedings of the ACM/SIGDA international symposium on Field programmable gate arrays10.1145/2435264.2435287(125-134)Online publication date: 11-Feb-2013
https://dl.acm.org/doi/10.1145/2435264.2435287
Zhang YQu PQian ZWang HZheng W(2013)Software/Hardware Hybrid Network-on-Chip Simulation on FPGAProceedings of the 10th IFIP International Conference on Network and Parallel Computing - Volume 814710.1007/978-3-642-40820-5_15(167-178)Online publication date: 19-Sep-2013
https://dl.acm.org/doi/10.1007/978-3-642-40820-5_15
Liu PLiu YXia BXiang CWang XWu KWang WYao Q(2011)A networks-on-chip emulation/verification frameworkInternational Journal of High Performance Systems Architecture10.1504/IJHPSA.2011.0380533:1(2-11)Online publication date: 1-Jan-2011
https://dl.acm.org/doi/10.1504/IJHPSA.2011.038053
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