NoCGEN: A Template Based Reuse Methodology for Networks on Chip Architecture

In this paper, we describe NoCGEN, a Network On Chip (NoC)generator, which is used to create a simulatable and synthesizable NoC description. NoCGEN uses a set of modularisedrouter components that can be used to form different routerswith a varying number of ports, routing algorithms, data widthsand buffer depths. A graph description representing the inter-connection between these routers is used to generate a top-levelVHDL description.A wormhole output-queued 2-D mesh router was created toverify the capability of NoCGEN. Various parameterized designs were synthesized to provide estimated gate counts of 129Kto 695K for a number of topologies varying from a 2 x 2 meshto a 4x4 mesh, with constant data bus size width of 32. TheNoC was simulated with random traffic using a mixed SystemC/ VHDL environment to ensure correctness of operation and toobtain performance and average latency. The results show anaccepted load of 53% to 55.6% with an increase in buffer depthfrom 8 to 32 flits for the 4x4 mesh router.