Article

×pipesCompiler: A Tool for Instantiating Application Specific Networks on Chip

Authors:

Antoine Jalabert,

Srinivasan Murali,

Giovanni De MicheliAuthors Info & Claims

DATE '04: Proceedings of the conference on Design, automation and test in Europe - Volume 2

Page 20884

Published: 16 February 2004 Publication History

Abstract

Future Systems on Chips (SoCs) will integrate a large number of processor and storage cores onto a single chip and require Networks on Chip (NoC) to support the heavy communication demands of the system. The individual components of the SoCs will be heterogeneous in nature with widely varying functionality and communication requirements. The communication infrastructure should optimally match communication patterns among these components accounting for the individual component needs. In this paper we present xpipes Compiler, a tool for automatically instantiating an application-specific NoC for heterogeneous Multi-Processor SoCs. The xpipes Compiler instantiates a network of building blocks from a library of composable soft macros (switches, network interfaces and links) described in SystemC at the cycle-accurate level. The network components are optimized for that particular network and support reliable, latency-insensitive operation. Example systems with application-specific NoCs built using the xpipes Compiler show large savings in area (factor of 6.5), power (factor of 2.4) and latency (factor of 1.42) when compared to a general-purpose mesh-based NoC architecture.

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Cited By

Meyer BHartman AThomas D(2014)Cost-effective lifetime and yield optimization for NoC-based MPSoCsACM Transactions on Design Automation of Electronic Systems10.1145/253557519:2(1-33)Online publication date: 28-Mar-2014
https://dl.acm.org/doi/10.1145/2535575
Raina AMuthukumar V(2011)A unified design space simulation environment for network-on-chip: fuse-NInternational Journal of High Performance Systems Architecture10.1504/IJHPSA.2011.0380553:1(23-32)Online publication date: 1-Jan-2011
https://dl.acm.org/doi/10.1504/IJHPSA.2011.038055
Jafari FLu ZJantsch AYaghmaee MDe Micheli GAl-Hashimi BMueller WMacii E(2010)Optimal regulation of traffic flows in networks-on-chipProceedings of the Conference on Design, Automation and Test in Europe10.5555/1870926.1871317(1621-1624)Online publication date: 8-Mar-2010
https://dl.acm.org/doi/10.5555/1870926.1871317
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×pipesCompiler: A Tool for Instantiating Application Specific Networks on Chip

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cover image ACM Conferences

DATE '04: Proceedings of the conference on Design, automation and test in Europe - Volume 2

February 2004

606 pages

ISBN:0769520855

Copyright © Copyright (c) 2004 Institute of Electrical and Electronics Engineers, Inc. All rights reserved.

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SIGDA: ACM Special Interest Group on Design Automation

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IEEE Computer Society

United States

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Published: 16 February 2004

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DATE04: Design, Automation and Test in Europe 2004

February 16 - 20, 2004

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Overall Acceptance Rate 518 of 1,794 submissions, 29%

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Cited By

Meyer BHartman AThomas D(2014)Cost-effective lifetime and yield optimization for NoC-based MPSoCsACM Transactions on Design Automation of Electronic Systems10.1145/253557519:2(1-33)Online publication date: 28-Mar-2014
https://dl.acm.org/doi/10.1145/2535575
Raina AMuthukumar V(2011)A unified design space simulation environment for network-on-chip: fuse-NInternational Journal of High Performance Systems Architecture10.1504/IJHPSA.2011.0380553:1(23-32)Online publication date: 1-Jan-2011
https://dl.acm.org/doi/10.1504/IJHPSA.2011.038055
Jafari FLu ZJantsch AYaghmaee MDe Micheli GAl-Hashimi BMueller WMacii E(2010)Optimal regulation of traffic flows in networks-on-chipProceedings of the Conference on Design, Automation and Test in Europe10.5555/1870926.1871317(1621-1624)Online publication date: 8-Mar-2010
https://dl.acm.org/doi/10.5555/1870926.1871317
Ludovici DGaydadjiev GGilabert FGomez MBertozzi DPalesi MKumar SLu ZOgras U(2010)Contrasting topologies for regular interconnection networks under the constraints of nanoscale silicon technologyProceedings of the Third International Workshop on Network on Chip Architectures10.1145/1921249.1921259(37-42)Online publication date: 4-Dec-2010
https://dl.acm.org/doi/10.1145/1921249.1921259
De Micheli GSeiculescu CMurali SBenini LAngiolini FPullini ASapatnekar S(2010)Networks on ChipsProceedings of the 47th Design Automation Conference10.1145/1837274.1837352(300-305)Online publication date: 13-Jun-2010
https://dl.acm.org/doi/10.1145/1837274.1837352
Leary GChatha KRosenstiel WWakabayashi K(2009)Automated technique for design of NoC with minimal communication latencyProceedings of the 7th IEEE/ACM international conference on Hardware/software codesign and system synthesis10.1145/1629435.1629499(471-480)Online publication date: 11-Oct-2009
https://dl.acm.org/doi/10.1145/1629435.1629499
Sethuraman BVemuri RLombardi FBhanja SMassoud YBahar R(2009)A methodology for application-specific NoC architecture generation in a dynamic task structure environmentProceedings of the 19th ACM Great Lakes symposium on VLSI10.1145/1531542.1531580(149-152)Online publication date: 10-May-2009
https://dl.acm.org/doi/10.1145/1531542.1531580
Yoo JYoo SChoi K(2009)Topology/floorplan/pipeline co-design of cascaded crossbar busIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2009.201744217:8(1034-1047)Online publication date: 1-Aug-2009
https://dl.acm.org/doi/10.1109/TVLSI.2009.2017442
Gilabert FMedardoni SBertozzi DBenini LGomez MLopez PDuato J(2008)Exploring High-Dimensional Topologies for NoC Design Through an Integrated Analysis and Synthesis FrameworkProceedings of the Second ACM/IEEE International Symposium on Networks-on-Chip10.5555/1397757.1397991(107-116)Online publication date: 7-Apr-2008
https://dl.acm.org/doi/10.5555/1397757.1397991
Stensgaard MSparsø J(2008)ReNoCProceedings of the Second ACM/IEEE International Symposium on Networks-on-Chip10.5555/1397757.1397985(55-64)Online publication date: 7-Apr-2008
https://dl.acm.org/doi/10.5555/1397757.1397985
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