Article

Synthesis of synchronous assertions with guarded atomic actions

Authors:

M. Pellauer,

M. Lis,

D. Baltus,

R. NikhilAuthors Info & Claims

MEMOCODE '05: Proceedings of the 2nd ACM/IEEE International Conference on Formal Methods and Models for Co-Design

Pages 15 - 24

https://doi.org/10.1109/MEMCOD.2005.1487886

Published: 11 July 2005 Publication History

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Abstract

The SystemVerilog standard introduces SystemVerilog Assertions (SVA), a synchronous assertion package based on the temporal-logic semantics of PSL. Traditionally assertions are checked in software simulation. We introduce a method for synthesizing SVA directly into hardware modules in Bluespec SystemVerilog. This opens up new possibilities for FPGA-accelerated testbenches, hardware/software co-emulation, dynamic verification and fault-tolerance. We describe adding synthesizable assertions to a cache controller, and investigate their hardware cost.

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Witharana HLyu YCharles SMishra P(2022)A Survey on Assertion-based Hardware VerificationACM Computing Surveys10.1145/351057854:11s(1-33)Online publication date: 9-Sep-2022
https://dl.acm.org/doi/10.1145/3510578
Manerkar YLustig DMartonosi MPellauer MHunter HMoreno JEmer JSanchez D(2017)RTLcheckProceedings of the 50th Annual IEEE/ACM International Symposium on Microarchitecture10.1145/3123939.3124536(463-476)Online publication date: 14-Oct-2017
https://dl.acm.org/doi/10.1145/3123939.3124536
Curreri JStitt GGeorge A(2011)High-level synthesis of in-circuit assertions for verification, debugging, and timing analysisInternational Journal of Reconfigurable Computing10.1155/2011/4068572011(1-17)Online publication date: 1-Jan-2011
https://dl.acm.org/doi/10.1155/2011/406857
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We present CHA, an assertion language and verification tool for Chisel programs built on top of ChiselTest, where we extend the Chisel assertion language with SystemVerilog assertions (SVA)-like temporal operators. This enables formal verification ...

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MEMOCODE '05: Proceedings of the 2nd ACM/IEEE International Conference on Formal Methods and Models for Co-Design

July 2005

241 pages

ISBN:0780392272

Publisher

IEEE Computer Society

United States

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Published: 11 July 2005

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Overall Acceptance Rate 34 of 82 submissions, 41%

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Witharana HLyu YCharles SMishra P(2022)A Survey on Assertion-based Hardware VerificationACM Computing Surveys10.1145/351057854:11s(1-33)Online publication date: 9-Sep-2022
https://dl.acm.org/doi/10.1145/3510578
Manerkar YLustig DMartonosi MPellauer MHunter HMoreno JEmer JSanchez D(2017)RTLcheckProceedings of the 50th Annual IEEE/ACM International Symposium on Microarchitecture10.1145/3123939.3124536(463-476)Online publication date: 14-Oct-2017
https://dl.acm.org/doi/10.1145/3123939.3124536
Curreri JStitt GGeorge A(2011)High-level synthesis of in-circuit assertions for verification, debugging, and timing analysisInternational Journal of Reconfigurable Computing10.1155/2011/4068572011(1-17)Online publication date: 1-Jan-2011
https://dl.acm.org/doi/10.1155/2011/406857
Patel HShukla SLauwereins RMadsen J(2007)Tackling an abstraction gapProceedings of the conference on Design, automation and test in Europe10.5555/1266366.1266426(279-284)Online publication date: 16-Apr-2007
https://dl.acm.org/doi/10.5555/1266366.1266426
Long JSeawright ALevitan S(2007)Synthesizing SVA local variables for formal verificationProceedings of the 44th annual Design Automation Conference10.1145/1278480.1278500(75-80)Online publication date: 4-Jun-2007
https://dl.acm.org/doi/10.1145/1278480.1278500
Das SMohanty RDasgupta PChakrabarti PGielen G(2006)Synthesis of system verilog assertionsProceedings of the conference on Design, automation and test in Europe: Designers' forum10.5555/1131355.1131371(70-75)Online publication date: 6-Mar-2006
https://dl.acm.org/doi/10.5555/1131355.1131371
(2006)A rule-based model of computation for SystemCProceedings of the Fourth ACM/IEEE International Conference on Formal Methods and Models for Co-Design10.1109/MEMCOD.2006.1695899(39-48)Online publication date: 1-Jan-2006
https://dl.acm.org/doi/10.1109/MEMCOD.2006.1695899

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Automatic synthesis of cache-coherence protocol processors using Bluespec

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Automatic synthesis of cache-coherence protocol processors using Bluespec

Untwist your brain: efficient debugging and diagnosis of complex assertions

CHA: Supporting SVA-Like Assertions in Formal Verification of Chisel Programs (Tool Paper)

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