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High-level synthesis of in-circuit assertions for verification, debugging, and timing analysis

Published: 01 January 2011 Publication History

Abstract

Despite significant performance and power advantages compared to microprocessors, widespread usage of FPGAs has been limited by increased design complexity. High-level synthesis (HLS) tools have reduced design complexity but provide limited support for verification, debugging, and timing analysis. Such tools generally rely on inaccurate software simulation or lengthy register transfer-level simulations, which are unattractive to software developers. In this paper, we introduce HLS techniques that allow application designers to efficiently synthesize commonly used ANSI-C assertions into FPGA circuits, enabling verification and debugging of circuits generated from HLS tools, while executing in the actual FPGA environment. To verify that HLS-generated circuits meet execution timing constraints, we extend the in-circuit assertion support for testing of elapsed time for arbitrary regions of code. Furthermore, we generalize timing assertions to transparently provide hang detection that back annotates hang occurrences to source code. The presented techniques enable software developers to rapidly verify, debug, and analyze timing for FPGA applications, while reducing frequency by less than 3% and increasing FPGA resource utilization by 0.7% or less for several application case studies on the Altera Stratix-II EP2S180 and Stratix-III EP3SE260 using Impulse-C. The presented techniques reduced area overhead by as much as 3x and improved assertion performance by as much as 100% compared to unoptimized in-circuit assertions.

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Cited By

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  • (2018)Enhancing debug observability for HLS-based FPGA circuits through source-to-source compilationJournal of Parallel and Distributed Computing10.1016/j.jpdc.2018.02.012117:C(148-160)Online publication date: 1-Jul-2018
  • (2017)Transparent In-Circuit Assertions for FPGAsIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2016.261886236:7(1193-1202)Online publication date: 16-Jun-2017
  • (2015)In-circuit temporal monitors for runtime verification of reconfigurable designsProceedings of the 52nd Annual Design Automation Conference10.1145/2744769.2744856(1-6)Online publication date: 7-Jun-2015
  • Show More Cited By

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  1. High-level synthesis of in-circuit assertions for verification, debugging, and timing analysis

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        Published In

        cover image International Journal of Reconfigurable Computing
        International Journal of Reconfigurable Computing  Volume 2011, Issue
        Special issue on selected papers from the 17th reconfigurable architectures workshop (RAW2010)
        January 2011
        60 pages
        ISSN:1687-7195
        EISSN:1687-7209
        Issue’s Table of Contents

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        Hindawi Limited

        London, United Kingdom

        Publication History

        Published: 01 January 2011
        Accepted: 14 December 2010
        Received: 13 August 2010

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        View all
        • (2018)Enhancing debug observability for HLS-based FPGA circuits through source-to-source compilationJournal of Parallel and Distributed Computing10.1016/j.jpdc.2018.02.012117:C(148-160)Online publication date: 1-Jul-2018
        • (2017)Transparent In-Circuit Assertions for FPGAsIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2016.261886236:7(1193-1202)Online publication date: 16-Jun-2017
        • (2015)In-circuit temporal monitors for runtime verification of reconfigurable designsProceedings of the 52nd Annual Design Automation Conference10.1145/2744769.2744856(1-6)Online publication date: 7-Jun-2015
        • (2014)Using statistical assertions to guide self-adaptive systemsInternational Journal of Reconfigurable Computing10.1155/2014/7245852014(9-9)Online publication date: 1-Jan-2014

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