Witharana H, Lyu Y, Charles S and Mishra P.
(2022). A Survey on Assertion-based Hardware Verification. ACM Computing Surveys. 54:11s. (1-33). Online publication date: 31-Jan-2022.
Manerkar Y, Lustig D, Martonosi M and Pellauer M. RTLcheck. Proceedings of the 50th Annual IEEE/ACM International Symposium on Microarchitecture. (463-476).
Curreri J, Stitt G and George A.
(2011). High-level synthesis of in-circuit assertions for verification, debugging, and timing analysis. International Journal of Reconfigurable Computing. 2011. (1-17). Online publication date: 1-Jan-2011.
Long J and Seawright A. Synthesizing SVA local variables for formal verification. Proceedings of the 44th annual Design Automation Conference. (75-80).
Das S, Mohanty R, Dasgupta P and Chakrabarti P. Synthesis of system verilog assertions. Proceedings of the conference on Design, automation and test in Europe: Designers' forum. (70-75).
A rule-based model of computation for SystemC. Proceedings of the Fourth ACM/IEEE International Conference on Formal Methods and Models for Co-Design. (39-48).