research-article

Comparative study of power-gating architectures for nonvolatile FinFET-SRAM using spintronics-based retention technology

Authors:

Shuu'ichirou Yamamoto, and

Satoshi SugaharaAuthors Info & Claims

DATE '15: Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition

March 2015

Pages 866 - 871

Published: 09 March 2015 Publication History

Abstract

Power-gating (PG) architectures employing nonvolatile state/data retention are expected to be a highly efficient energy reduction technique for high-performance CMOS logic systems. Recently, two types of PG architectures using nonvolatile retention have been proposed: One architecture is nonvolatile PG (NVPG) using nonvolatile bistable circuits such as nonvolatile SRAM (NV-SRAM) and nonvolatile flip-flop (NV-FF), in which nonvolatile retention is not utilized during the normal SRAM/FF operation mode and it is used only when there exist energetically meaningful shutdown periods given by break-even time (BET). In contrast, the other architecture employs nonvolatile retention during the normal SRAM/FF operation mode. In this type of architecture, an even short standby period can be replaced by a shutdown period, and thus this architecture is also called normally-off (NOF) rather than PG. In this paper, these two PG architectures for a FinFET-based high-performance NV-SRAM cell employing spintronics-based nonvolatile retention were systematically analyzed using HSPICE with a magnetoresistive-device macromodel. The NVPG architecture shows effective reduction of energy dissipation without performance degradation, whereas the NOF architecture causes severe performance degradation and the energy efficiency of the NOF architecture cannot be superior to that of the NVPG architecture.

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Cited By

Kang WLv WZhang YZhao W(2017)Low Store Power High-Speed High-Density Nonvolatile SRAM Design With Spin Hall Effect-Driven Magnetic Tunnel JunctionsIEEE Transactions on Nanotechnology10.1109/TNANO.2016.264033816:1(148-154)Online publication date: 1-Jan-2017
https://dl.acm.org/doi/10.1109/TNANO.2016.2640338
Shuto YYamamoto SSugahara S(2016)Design and implementation of nonvolatile power-gating SRAM using SOTB technologyProceedings of the 2016 International Symposium on Low Power Electronics and Design10.1145/2934583.2934628(338-343)Online publication date: 8-Aug-2016
https://dl.acm.org/doi/10.1145/2934583.2934628

Index Terms

Comparative study of power-gating architectures for nonvolatile FinFET-SRAM using spintronics-based retention technology
1. Hardware
  1. Hardware validation
  2. Integrated circuits
    1. Semiconductor memory
      1. Static memory

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Information

Published In

cover image ACM Conferences

DATE '15: Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition

March 2015

1827 pages

ISBN:9783981537048

General Chair:
Wolfgang Nebel
OFFIS & University of Oldenburg, DE
,
Program Chair:
David Atienza
EPFL, CH

Sponsors

EDAA: European Design Automation Association
ECSI
EDAC: Electronic Design Automation Consortium
SIGDA: ACM Special Interest Group on Design Automation
Russian Acadamy of Sciences: Russian Acadamy of Sciences
IEEE Council on Electronic Design Automation (CEDA)

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EDA Consortium

San Jose, CA, United States

Publication History

Published: 09 March 2015

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DATE '15

Sponsor:

EDAA
EDAC
SIGDA
Russian Acadamy of Sciences

DATE '15: Design, Automation and Test in Europe

March 9 - 13, 2015

Grenoble, France

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DATE '15 Paper Acceptance Rate 206 of 915 submissions, 23%;

Overall Acceptance Rate 518 of 1,794 submissions, 29%

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Cited By

Kang WLv WZhang YZhao W(2017)Low Store Power High-Speed High-Density Nonvolatile SRAM Design With Spin Hall Effect-Driven Magnetic Tunnel JunctionsIEEE Transactions on Nanotechnology10.1109/TNANO.2016.264033816:1(148-154)Online publication date: 1-Jan-2017
https://dl.acm.org/doi/10.1109/TNANO.2016.2640338
Shuto YYamamoto SSugahara S(2016)Design and implementation of nonvolatile power-gating SRAM using SOTB technologyProceedings of the 2016 International Symposium on Low Power Electronics and Design10.1145/2934583.2934628(338-343)Online publication date: 8-Aug-2016
https://dl.acm.org/doi/10.1145/2934583.2934628

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